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  1. 1
    Challenges of hidden data in the unused area two within executable files

    Challenges of hidden data in the unused area two within executable files by Naji, Ahmed Wathik, Zaidan, A.A., Zaidan, B.B.

    Published 2009
    “…There are many challenges of hidden data in the unused area two within executable files, which is dependencies of the size of the cover file with the size of hidden information, differences of the size of file before and after the hiding process, availability of the cover file after the hiding process to perform normally and detection by antivirus software as a result of changes made to the file. Approach: The system designed to accommodate the release mechanism that consists of two functions; first is the hiding of the information in the unused area 2 of PE-file (exe.file), through the execution of four process (specify the cover file, specify the information file, encryption of the information, and hiding the information) and the second function is the extraction of the hiding information through three process (specify the steno file, extract the information, and decryption of the information). …”
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  2. 2
    Direct approach for mining association rules from structured XML data

    Direct approach for mining association rules from structured XML data by Abazeed, Ashraf Riad

    Published 2012
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    Thesis
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  3. 3
    Hardware Implementation Of Modified A5/1 Stream Cipher

    Hardware Implementation Of Modified A5/1 Stream Cipher by Siti Yohana Akmal Mohd Fauzi, Kamaruzzaman Seman, Marinah Othman, Farrah Masyitah Mohd Shuib

    Published 2024
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  4. 4
    RISC-V instruction set extension on blockchain application

    RISC-V instruction set extension on blockchain application by Cheong , Kin Seng

    Published 2024
    “…However, blockchain required a high computing power to function. Although there were numerous ways to improve the performance speed of blockchain technology in software implementations, hardware implementation of the blockchain algorithms was a more preferred choice due to the emerging open-source computer architecture, RISC-V. …”
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  5. 5
    Design Methodology and Analysis of Hash Function based-on Field Programmable Gate Array for Hash-based Message Authentication Code Application

    Design Methodology and Analysis of Hash Function based-on Field Programmable Gate Array for Hash-based Message Authentication Code Application by SHAMSIAH BINTI, SUHAILI

    Published 2025
    “…For this purpose, cryptography hash functions are selected as a design target. These algorithms have been studied to improve the speed, area implementation, and power consumption. …”
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  6. 6
    Prevention And Detection Mechanism For Security In Passive Rfid System

    Prevention And Detection Mechanism For Security In Passive Rfid System by Khor, Jing Huey

    Published 2013
    “…A GUI is created in a form of JAVA application to display data detected from tag. …”
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  7. 7
    Automatic generation of content security policy to mitigate cross site scripting

    Automatic generation of content security policy to mitigate cross site scripting by Mhana, Samer Attallah, Din, Jamilah, Atan, Rodziah

    Published 2016
    “…The algorithm is implemented as a plugin. It does not interfere with the web application original code. …”
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  8. 8
    Studies on flat CORDIC implementation in field programmable gate arrays (FPGA) / Meera Subramaniam

    Studies on flat CORDIC implementation in field programmable gate arrays (FPGA) / Meera Subramaniam by Meera , Subramaniam

    Published 2004
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  9. 9
    Development of low power viterbi decoder on complex programmable logic device platform

    Development of low power viterbi decoder on complex programmable logic device platform by Abu, Mohd Azlan

    Published 2018
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  10. 10
    IMAGE PROCESSING ALGORITHMS ON FPGA

    IMAGE PROCESSING ALGORITHMS ON FPGA by MOHAMED SHUKOR, MOHAMED NASIR

    Published 2007
    “…The objective of this project is to construct a real time hardware image processing system which based on Field Programmable Gate Array (FPGA). …”
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    Final Year Project
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  11. 11
    Implementation of Color Filtering on FPGA

    Implementation of Color Filtering on FPGA by Mohd Shukor, Mohd Nasir, Lo, H. H., Sebastian, Patrick

    Published 2007
    “…The chosen image processing algorithm is a single Color Filtering algorithm. This work utilizes Altera DE2 development board empowered by the Cyclone II FPGA paired with a 1.3 Mega pixel CMOS camera from Terasik Technologies. …”
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  12. 12
    Adaptable algorithms for performance optimization of dynamic batch manufacturing processes

    Adaptable algorithms for performance optimization of dynamic batch manufacturing processes by Teo, Kenneth Tze Kin

    Published 2018
    “…Various algorithms are designed, formulated and computed in MATLAB and then embedded to a real-time programmable microcontroller. …”
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  13. 13
    VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM

    VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM by Erdogan, S. S., Abdul Rahman, Abdul Wahab, T., H. Hong

    Published 1993
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  14. 14
    Implementation of integral control state feedback controller on prasmatic control of universal strech and bending machine (USBM) simplified model

    Implementation of integral control state feedback controller on prasmatic control of universal strech and bending machine (USBM) simplified model by Nik Mohd. Farhan, Abd Wahab

    Published 2008
    “…It is important to verify simulation result through experiment and compare it with expected result. As we know, many functions can be implemented using Programmable Logic Controller (PLC). …”
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    Undergraduates Project Papers
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  15. 15
    Developed method of FPGA-based fuzzy logic controller design with the aid of conventional PID algorithm

    Developed method of FPGA-based fuzzy logic controller design with the aid of conventional PID algorithm by Obaid, Zeyad Assi, Sulaiman, Nasri, Hamidon, Mohd Nizar

    Published 2009
    “…This method also enables us to design the controller to work as PDFLC, PIFLC or PIDFLC depending on two (one-bit) external signals with programmable fuzzy sets and programmable rule table using VHDL language for implementation on FPGA device, and to employ the new technique of fuzzy algorithm in order to serve a wide range of the physical systems which require a real-time operation. …”
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  16. 16
    Improved genetic algorithm for direct current motor high speed controller implemented on field programmable gate array

    Improved genetic algorithm for direct current motor high speed controller implemented on field programmable gate array by Alkhafaji, Falih Salih

    Published 2019
    “…On the one side, the estimation Transfer Function (TF) of these motors is considered a significant problem in most previous studies which causes bad controller design, if the low estimation accuracy. …”
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  17. 17
    Design and implementation of multimedia digital matrix system

    Design and implementation of multimedia digital matrix system by Chui, Yew Leong, Ramli, Abdul Rahman, Perumal, Thinagaran, Sulaiman, Mohd Yusof, Ali, Mohd Liakot

    Published 2005
    “…Due to the issues of signal integrity in high-speed digital design, a new adaptive channel synchronization algorithm has been developed. …”
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  18. 18
    Reusable data-path architecture for encryption-then-authentication on FPGA

    Reusable data-path architecture for encryption-then-authentication on FPGA by Abbas Y.A., Jidin R., Jamil N., Zaba M.R.

    Published 2023
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  19. 19
    Implementing wireless monitoring for substations on the field programmable logic arrays (FPGA)

    Implementing wireless monitoring for substations on the field programmable logic arrays (FPGA) by Jidin R., Syuhada Y., Mohd A., Yee L.T.

    Published 2023
    Conference paper
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  20. 20
    Implementation of color filtering on FPGA

    Implementation of color filtering on FPGA by P., Sebastian, M.N.B.M., Shukor, H.H., Lo

    Published 2007
    “…The chosen image processing algorithm is a single Color Filtering algorithm. This work utilizes Altera DE2 development board empowered by the Cyclone II FPGA paired with a 1.3 Mega pixel CMOS camera from Terasik Technologies. …”
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