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  1. 1
    Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation

    Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation by Ismail, Mohd. Izuan

    Published 2006
    “…The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). The processor design is completely described in hardware description language, VHDL. …”
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  2. 2
    Sigma-delta analog to digital converter on field programmable gate array

    Sigma-delta analog to digital converter on field programmable gate array by Hamadani, Maral Faghani

    Published 2015
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  3. 3
    Design of field programmable gate array-based proportional-integral-derivative fuzzy logic controller with tunable ganin

    Design of field programmable gate array-based proportional-integral-derivative fuzzy logic controller with tunable ganin by Obaid, Zeyad Assi

    Published 2010
    “…Many of fuzzy control applications require real-time operation; higher density programmable logic devices such as Field Programmable Gate Array (FPGA) can be used to integrate large amounts of logic in a single IC. …”
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  4. 4
    Design Of Direct Sequence Code Division Multiple Access (Ds-Cdma) Wireless Transmitter Using Field Programmable Gate Array (Fpga)

    Design Of Direct Sequence Code Division Multiple Access (Ds-Cdma) Wireless Transmitter Using Field Programmable Gate Array (Fpga) by Osman, Khalid Eltahir Mohamed

    Published 2002
    “…This thesis describes the DS-CDMA wireless transmitter design using FPGA (Field Programmable Gate Array), which has been adopted in many wireless access technologies. …”
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  5. 5
    Implementation of a low complexity peak-to-average power ratio reduction scheme on field programmable gate array

    Implementation of a low complexity peak-to-average power ratio reduction scheme on field programmable gate array by Varahram, Pooria, Mohd Ali, Borhanuddin

    Published 2015
    “…Here implementation of a proposed PTS on field programmable gate array platform to show the feasibility of the PAPR reduction scheme is carried out. …”
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  6. 6
    Hardware Implementation Of Modified A5/1 Stream Cipher

    Hardware Implementation Of Modified A5/1 Stream Cipher by Siti Yohana Akmal Mohd Fauzi, Kamaruzzaman Seman, Marinah Othman, Farrah Masyitah Mohd Shuib

    Published 2024
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  7. 7
    FPGA based Twofish Algorithm

    FPGA based Twofish Algorithm by Muhammad Imran, Ahmad, Mohd Nazrin, Md Isa, Abdul Halis, Abdul Aziz, Mohd Fisol, Osman

    Published 2009
    “…This paper presents the architecture of Twofish algorithm implemented with field programmable gate array (FPGA). Twofish is one of the five finalists in AES contest. …”
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  8. 8
    Design and implementation of real data fast fourier transform processor on field programmable gates array

    Design and implementation of real data fast fourier transform processor on field programmable gates array by Ahmed, Mohammed Kassim

    Published 2015
    “…In this work, the memorybased FFT processor, based on radix-4 FFT algorithm is implemented on Cyclone II Field Programmable Gates Array (FPGA). In order to program the FPGA, Verilog Hardware Description Language (Verilog HDL) is used. …”
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  9. 9
    Design method to transmit and receive source synchronous signals using source asynchronous

    Design method to transmit and receive source synchronous signals using source asynchronous by Ramachandran, Nathan

    Published 2013
    “…Penyelesaian yang dicadangkan juga akan membolehkan jarak penghantaran saluran jam yang lebih panjang digunakan. Lower cost Field Programmable Gate Array (FPGA) devices offer limited data rate speed for source synchronous Low-Voltage Differential Signaling (LVDS) Input-Output (IO) interfaces but higher data rate speeds for source asynchronous transceivers channels. …”
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  10. 10
    Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA

    Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA by Shahadi H.I., Jidin R., Way W.H.

    Published 2023
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  11. 11
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
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  12. 12
    Partial discharge detection system for counting PD signals in high voltage underground cable by using FPGA technology

    Partial discharge detection system for counting PD signals in high voltage underground cable by using FPGA technology by Emilliano, Chakrabarty C.K., Ramasamy A.K., Ghani A.B.A.

    Published 2023
    “…Currently, FPGA (Field Programmable Gate Array) technology is being widely used for signal processing and control owing to its fast digital processing capability. …”
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  13. 13
    Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform

    Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform by Hamza, Ekhlas Kadhum

    Published 2011
    “…Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs) and general-purpose processors (GPPs) designs are viable solution for software defined radio (SDR) technology. …”
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  14. 14
    FPGA implementation of MCPFSK modulation for HF data communication

    FPGA implementation of MCPFSK modulation for HF data communication by Fitri Dewi, Jaswar, Ahmad Zuri, Sha’ameri

    Published 2009
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  15. 15
    Embedded System Real Time Data Acquisition System Using FPGA Technology for Detection and Counting of PD Signal from PICO Pulse Generator

    Embedded System Real Time Data Acquisition System Using FPGA Technology for Detection and Counting of PD Signal from PICO Pulse Generator by Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Suhendi N.

    Published 2023
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  16. 16
    Flood Monitoring Warning System using FPGA / Ahmad Al-Zubir Zulkifly

    Flood Monitoring Warning System using FPGA / Ahmad Al-Zubir Zulkifly by Zulkifly, Ahmad Al-Zubir

    Published 2012
    “…The heart of the design is described using Verilog HDL (Hardware Description Language) and implemented in hardware using Field Programmable Gate Array (FPGA). This design is prototyped on Altera`s Cyclone DE2 FPGA board.…”
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  17. 17
    Optimized Encoder Architecture for Structured Low Density Parity Check Codes of Short Length

    Optimized Encoder Architecture for Structured Low Density Parity Check Codes of Short Length by Anggraeni, Silvia, Hussin, Fawnizu Azmadi, Jeoti , Varun

    Published 2014
    “…The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. …”
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  18. 18
    Performance of MIMO DWT for millimeter wave communication system

    Performance of MIMO DWT for millimeter wave communication system by Parveen, Nagma, Abdullah, Khaizuran, Islam, Md. Rafiqul, Boby, Rounakul Islam

    Published 2019
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  19. 19
    Optimized encoder architecture for structured low density parity check codes of short length

    Optimized encoder architecture for structured low density parity check codes of short length by Anggraeni, S., Hussin, F.A., Jeoti, V.

    Published 2014
    “…The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. …”
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  20. 20
    Design and implementation of low complexity OFDM modulator for broadband wireless devices

    Design and implementation of low complexity OFDM modulator for broadband wireless devices by Al-Hussaini, Khalid Taher Mohammed

    Published 2017
    “…This research presents three novel low complexity techniques for reducing CF in OFDM systems followed by an efficient hardware co-simulation implementation of two of these techniques by using a Xilinx system generator on a field programmable gate array (FPGA). The first part of this thesis presents a new subblocks interleaving partial transmit sequence (SBI-PTS) technique having low complexity for reducing the CF in OFDM systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on a field programmable gate array (FPGA). …”
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