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Hardware Implementation Of Modified A5/1 Stream Cipher by Siti Yohana Akmal Mohd Fauzi, Kamaruzzaman Seman, Marinah Othman, Farrah Masyitah Mohd Shuib

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Design of field programmable gate array-based proportional-integral-derivative fuzzy logic controller with tunable ganin by Obaid, Zeyad Assi

“…Many of fuzzy control applications require real-time operation; higher density programmable logic devices such as Field Programmable Gate Array (FPGA) can be used to integrate large amounts of logic in a single IC. …”
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FPGA based Twofish Algorithm by Muhammad Imran, Ahmad, Mohd Nazrin, Md Isa, Abdul Halis, Abdul Aziz, Mohd Fisol, Osman

“…This paper presents the architecture of Twofish algorithm implemented with field programmable gate array (FPGA). Twofish is one of the five finalists in AES contest. …”
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Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA by Shahadi H.I., Jidin R., Way W.H.

Design method to transmit and receive source synchronous signals using source asynchronous by Ramachandran, Nathan

“…Cyclone V which is a low cost FPGA device supports LVDS IO channels for data rates up-till 1.25 Gigabit per second (Gbps) meanwhile the transceiver channels support data rates up-till 5 Gbps. …”
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Embedded System Real Time Data Acquisition System Using FPGA Technology for Detection and Counting of PD Signal from PICO Pulse Generator by Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Suhendi N.

Partial discharge detection system for counting PD signals in high voltage underground cable by using FPGA technology by Emilliano, Chakrabarty C.K., Ramasamy A.K., Ghani A.B.A.

“…Currently, FPGA (Field Programmable Gate Array) technology is being widely used for signal processing and control owing to its fast digital processing capability. …”

Optimized Encoder Architecture for Structured Low Density Parity Check Codes of Short Length by Anggraeni, Silvia, Hussin, Fawnizu Azmadi, Jeoti , Varun

“…The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. …”
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Optimized encoder architecture for structured low density parity check codes of short length by Anggraeni, S., Hussin, F.A., Jeoti, V.

“…The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. …”
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Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach by Chew , Ming Choo

“…Secara tradisinya, “Field Programmable Gate Array” (FPGA) “Address Register” (AR) direka menggunakan “full custom”. …”
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A new torque and flux controller for direct torque control of induction machines by Nik Idris, Nik Rumzi, Chuen, Ling Toh, Elbuluk, Malik E.

“…The hardware implementation is mainly constructed by using DSP TMS320C31 and Altera field-programmable gate array devices. The results prove that a significant torque and stator flux ripples reduction is achieved. …”
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Implementation On UTeMRISC Microcontroller With Embedded Fault-Tolerance by Mohd Hafiz, Sulaiman, Sani Irwan, Md Salim, Masrullizam, Mat Ibrahim

“…The design is focused on the implementation of Hamming Code and Single-Error-Correction Double-Error-Detection (SEC-DED) Code that are synthesizable in the Field Programmable Gate Array (FPGA). To evaluate the performance and functionality of the design, a number of pre-defined faults are injected into the Fault-Tolerant module at three different locations in the UTeMRISC Microcontroller architecture. …”
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FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices by Al-Shatari, M.O.A., Hussin, F.A., Aziz, A.A., Witjaksono, G., Tran, X.-T.

“…It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. …”
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Implementation of luo-rudi phase 1 cardiac cell excitation model in FPGA by Othman, Norliza

“…Due to the drawbacks, this research presents the adaptation of Luo-Rudy Phase I (LR-I) cardiac excitation model in a rapid prototyping method of field programmable gate array (FPGA) for real-time simulation, lower power consumption and minimizing the size. …”
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Power Amplifiers Linearization Based On Complex Gain Memory Predistortion by Varahram, Pooria

“…This complex divider is then designed and implemented in Field Programmable Gate Array (FPGA) and combined with other parts to make the predistortion block. …”
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FPGA-enabled binarised convolutional neural networks toward real-time embedded object recognition system by Shuto, Daisuke, Abbas, Z., Sulaiman, N., Tamukoh, H.

“…In this presentation, we report the results of applying a binarised Convolutional Neural Network (CNN) and a Field Programmable Gate Array (FPGA) for image-based object recognition. …”
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FPGA Based Individual Computer Architecture Laboratory Exercises by Othman Ahmad

“…Computer Architecture is a core subject for the Electronic (Computer) Engineering course at the Universiti Malaysia Sabah that is compliant to the requirement of the Washington Accord as accredited by the Engineering Accreditation Council of the Board of Engineers of Malaysia (EAC). An FPGA (Field Programmable Gate Array) based Computer Architecture Laboratory had been developed to support the curriculum of this course. …”
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A Simple Approach of Space-vector Pulse Width Modulation Realization Based on Field Programmable Gate Array by Sutikno, Tole, Jidin, Auzani, Wong, Jenn Hwa, Nik Idris, Nik Rumzi

“…Employing a field programmable gate array to realize space-vector pulse width modulation is a solution to boost system performance. …”
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Implementation study of field programmable gate array (FPGA) and complex programmable logic device (CPLD) in collision avoidance system using vhsic hardware description language (V... by Mohammad Naqiuddin Fahmi, Fathli, Zulkifli, Md. Yusof

“…In this collision avoidance system, there will be uses of Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD). …”
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Design of large built-in self-test programmable logic arrays by Zahari Mohamed Darus, Iftekhar Ahmed

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