Search Results - (( program visualisation based algorithm ) OR ( its implementation level algorithm ))

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  1. 1

    Reconstruction algorithm of calibration map for RPT technique in quadrilateral bubble column reactor using MCNPX code by Mohd Yunos, Mohd Amirul Syafiq, Anak Usang, Mark Dennis, Ithnin, Hanafi, Hussain, Siti Aslina, Mohamed Yusoff, Hamdan, Sipaun, Susan

    Published 2018
    “…The result of the studies proved that higher number of particles used in the algorithm for position reconstruction gives more accuracy and we found that the Sc-46 obtain more accurate calculation and shows low statistical level than Au-198 particle. …”
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    Article
  2. 2

    Correlation analysis and predictive performance based on KNN and decision tree with augmented reality for nuclear primary cooling process / Ahmad Azhari Mohamad Nor by Mohamad Nor, Ahmad Azhari

    Published 2024
    “…Subsequently, predictive models employing k-nearest neighbour and decision tree algorithms are constructed and evaluated based on accuracy, precision, and recall metrics. …”
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    Thesis
  3. 3

    A simplified synchronous reference frame for indirect current controlled three-level inverter-based shunt active power filters by Hoon, Yap, Mohd Radzi, Mohd Amran, Hassan, Mohd Khair, Mailah, Nashiren Farzilah, Abdul Wahab, Noor Izzri

    Published 2016
    “…In its controller, the SRF algorithm which is derived based on the direct-quadrature (DQ) theory has played a significant role as a harmonics extraction algorithm due to its simple implementation features. …”
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    Article
  4. 4

    Three-phase three-level shunt active power filter with simplified synchronous reference frame by Hoon, Yap, Mohd Radzi, Mohd Amran, Hassan, Mohd Khair, Mailah, Nashiren Farzilah

    Published 2016
    “…Shunt active power filter (SAPF) is the most effective solution to current harmonics. In its controller, Synchronous Reference Frame (SRF) principle has widely been applied in current harmonics extraction algorithm due to its simple implementation features. …”
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    Conference or Workshop Item
  5. 5

    Register Transfer Level Implementation Of Pooling - Based Feature Extraction For Finger Vein Identification by Mohamed Ali, Mohamed Hassan

    Published 2017
    “…The proposed algorithm was implemented on hardware using Verilog-HDL, and targeting Field Programmable Gate Array (FPGA) applications. …”
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    Thesis
  6. 6

    FBGA-based implementation of electronic abacus using altera DE2 board by Sidek, Azmi

    Published 2017
    “…The electronic abacus is developed by integrating an abacus, abacus decoder module and FPGA-based processor. DE2 115 is chosen as the development module and VHDL as main programming language. …”
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    Thesis
  7. 7

    A genetic algorithm for solving single level lotsizing problems by Zenon, Nasaruddin, Ahmad, Ab. Rahman, Ali, Rosmah

    Published 2003
    “…In this paper a genetic algorithm for solving single level lot-sizing problems is proposed and the results of applying the algorithm toexample problems are discussed. …”
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    Article
  8. 8
  9. 9

    Implementation and Evaluation of Large Rsa Encryption and Decryption Keys For Internet Security by H. Belgassem, Seddeq

    Published 2004
    “…Performance has always been the most critical characteristic of a cryptographic algorithm, which determines its effectiveness. In this research the most popular and used algorithm, which is RSA, is implemented with a new modification in order to reduce the calculation time of the algorithm. …”
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    Thesis
  10. 10
  11. 11

    The AGEB Algorithm for Solving the Heat Equation in Three Space Dimensions and Its Parallelization Using PVM by Sahimi, Mohd Salleh, Alias, Norma, Sundararajan, Elankovan

    Published 2001
    “…It is inherently explicit and is therefore well suited for parallel implementation on the PVM where data decomposition is run asynchronously and concurrently at every time level. …”
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    Article
  12. 12

    BinDCT Design and Implementation on FPGA with Low Power Architecture by Jabbar, Mohamad Hairol

    Published 2008
    “…In this work, the design and implementation of 8 x 8 block 2-D forward BinDCT algorithm on a Field Programmable Gate Array (FPGA) is presented. …”
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    Thesis
  13. 13

    Combined heat and power (CHP) economic dispatch solved using Lagrangian relaxation with surrogate subgradient multiplier updates by Sashirekha A., Pasupuleti J., Moin N.H., Tan C.S.

    Published 2023
    “…Flexibility for the choice of algorithm is given at the lower levels optimization techniques with the condition that the algorithm is able to improve its search at each iteration. …”
    Article
  14. 14

    Dynamic traffic scheduling and resource reservation algorithms for output-buffered switches by Subramaniam, Shamala

    Published 2002
    “…Previously, this algorithm has been analysed for a unified resource reservation and scheduling algorithm while implementing a tail discarding strategy. …”
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    Thesis
  15. 15

    A self-tuning filter-based adaptive linear neuron approach for operation of three-level inverter-based shunt active power filters under non-ideal source voltage conditions by Yap, Hoon, Mohd Radzi, Mohd Amran, Hassan, Mohd Khair, Mailah, Nashiren Farzilah

    Published 2017
    “…Additionally, the proposed STF-based ADALINE algorithm implements the modified Widrow-Hoff (W-H) weight updating algorithm for fast generation of reference current. …”
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    Article
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    ANALYSIS AND INTERPRETATION OF PRESSURE TRANSIENT TEST DATA BY RECENT ROBUST DECONVOLUTION METHODS by Mohd Mustafa, Muhammad Izzatullah

    Published 2013
    “…Recently, the robust deconvolution algorithms that tolerate high levels of errors in pressure and rate than the previous deconvolution algorithms have been introduced in the literature. …”
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    Final Year Project
  18. 18

    Implementation of generalized predictive control (GPC) for a real-time process control using labview by Mohd. Faudzi, Ahmad 'Athif

    Published 2006
    “…LabVIEW is chosen because of its block diagram implementation with simple graphical user interface approach to execute algorithm in real-time faster. …”
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    Thesis
  19. 19

    The AGEB Algorithm for Solving the Heat Equation in Three Dimensions and Its Parallelization Using PVM by Sahimi, Mohd Salleh, Alias, Norma, Sundarajan, Elankovan

    Published 2001
    “…It is inherently explicit and is therefore well suited for parallel implementation on the PVM where data decomposition is run asynchronously and concurrently at every time level. …”
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    Article
  20. 20

    DC-link capacitor voltage regulation for three-phase three-level inverter-based shunt active power filter with inverted error deviation control by Yap, Hoon, Mohd Radzi, Mohd Amran, Hassan, Mohd Khair, Mailah, Nashiren Farzilah

    Published 2016
    “…A new control technique known as inverted error deviation (IED) control is incorporated into the main DC-link capacitor voltage regulation algorithm of a three-level neutral-point diode clamped (NPC) inverter-based shunt active power filter (SAPF) to enhance its performance in overall DC-link voltage regulation so as to improve its harmonics mitigation performances. …”
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    Article