Search Results - (( program implementation max algorithm ) OR ( parallel optimization bees algorithm ))
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1
Performance Comparison of Parallel Bees Algorithm on Rosenbrock Function
Published 2012“…This thesis presents the parallel Bees Algorithm as a new approach for optimizing the last results for the Bees Algorithm. …”
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2
Energy-aware scheduling optimization in hybrid flow shops using artificial bee colony algorithm
Published 2024“…Through an extensive computational experiment involving a well-known benchmark suite, the ABC algorithm demonstrated remarkable performance, consistently outperforming several popular metaheuristic algorithms, including Genetic Algorithms, Particle Swarm Optimization, Memetic Algorithms, and Whale Optimization Algorithm in 75% of the problems. …”
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3
A multidimensional data descriptor tool based on fuzzy min max neural network algorithm
Published 2018“…They have been compare for their advantages and disadvantages. The implementation of Fuzzy Min Max Neural Network technique has been applied using Matlab Programming. …”
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Undergraduates Project Papers -
4
An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations.
Published 2013“…This research has focused at developing a discrete-event simulator to implement bandwidth allocation algorithms for a WiMAX base station.The highest urgency first algorithm has been utilized as a benchmark deployment algorithm in order to provide: dynamic downlink/uplink adjustment and latency guarantee for real-time applications. …”
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5
Maximum 2-satisfiability in radial basis function neural network
Published 2020“…The simulated results suggest that the proposed algorithm is effective in doing MAX2SAT logic programming by analysing the performance by obtaining lower Root Mean Square Error, high ratio of satisfied clauses and lesser CPU time.…”
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6
Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array
Published 2008“…After modeling, the algorithm is implemented in DSP. By using the Hardware- In-Loop facility of DSP, the comparison between hardware implementation and software modeling is performed. …”
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7
Restoration planning strategy of transmission system based on optimal energizing time of sectionalizing islands / Dian Najihah Abu Talib
Published 2019“…There are two discrete optimization techniques used in this work, which are the Artificial Bee Colony algorithm and Evolutionary Programming. …”
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Designing and Developing an Intelligent Congkak
Published 2011“…and “Can Min-Max algorithm (MM) be speeded up by using NN as a forward-pruning method?”. …”
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10
CPLD based controller for single phase inverters
Published 2007“…A type of filter is used to improve the distortion in the output waveform. A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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11
CPLD based controller for single phase inverters
Published 2007“…A type of filter is used to improve the distortion in the output waveform. A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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12
Fast fourier transform processor implementation for high inputs on field programmable gates array
Published 2018“…Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. …”
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FPGA Implementation of Emergency Door Car Entry System
Published 2008“…Emergency door car entry system can be implemented using Field Programmable Gate Array (FPGA) board. …”
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Learning Object -
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SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment
Published 2024“…To conduct this experiment, we employed the CloudSim simulator, which is implemented using the Java programming language.…”
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15
Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture
Published 2001“…However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. …”
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