Search Results - (( program coding max algorithm ) OR ( java application mining algorithm ))

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  1. 1
    Direct approach for mining association rules from structured XML data

    Direct approach for mining association rules from structured XML data by Abazeed, Ashraf Riad

    Published 2012
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  2. 2
    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations.

    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations. by Naghshbandi, Danial, Subramaniam, Shamala, Moghadam, Saeed Rahimi

    Published 2013
    “…This research has focused at developing a discrete-event simulator to implement bandwidth allocation algorithms for a WiMAX base station.The highest urgency first algorithm has been utilized as a benchmark deployment algorithm in order to provide: dynamic downlink/uplink adjustment and latency guarantee for real-time applications. …”
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  3. 3
    Separator Database and SPM Tree Framework for Mining Sequential Patterns Using Prefixspan with Pseudoprojection

    Separator Database and SPM Tree Framework for Mining Sequential Patterns Using Prefixspan with Pseudoprojection by Saputra , Dhany, Rambli, Dayang R.A., Foong, Oi Mean

    Published 2008
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  4. 4
    Study and Implementation of Data Mining in Urban Gardening

    Study and Implementation of Data Mining in Urban Gardening by Mohana, Muniandy, Lee, Eu Vern

    Published 2019
    “…Attached sensors generate data and send these data to the Java Servlet application through a WIFI module. These data are processed and stored in appropriate formats in a MySQL server database. …”
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  5. 5
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
    “…To do so, the verilog code is written for programming the FPGA base on the signal which is come from DSP. …”
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  6. 6
    Mining Sequential Patterns Using I-PrefixSpan

    Mining Sequential Patterns Using I-PrefixSpan by Dhany , Saputra, Rambli Dayang, R.A., Foong, Oi Mean

    Published 2007
    “…Sequential pattern mining is a relatively new data-mining problem with many areas of application. …”
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  7. 7
    A web-based implementation of k-means algorithms

    A web-based implementation of k-means algorithms by Lee, Quan

    Published 2022
    “…This stinginess of proximity measures in data mining tools is stifling the performance of the algorithm. …”
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    Final Year Project / Dissertation / Thesis
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  8. 8
    Mining Sequential Patterns using I-PrefixSpan

    Mining Sequential Patterns using I-PrefixSpan by Saputra , Dhany, Dayang R.A. Rambli, Foong, Oi Mean

    Published 2008
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    Citation Index Journal
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  9. 9
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…FPGA board is a board that can be programmed using source code to run the application that has been downloaded into it. …”
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    Learning Object
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  10. 10
    Features selection for intrusion detection system using hybridize PSO-SVM

    Features selection for intrusion detection system using hybridize PSO-SVM by Tabaan, Alaa Abdulrahman

    Published 2016
    “…The simulation will be carried on WEKA tool, which allows us to call some data mining methods under JAVA environment. The proposed model will be tested and evaluated on both NSL-KDD and KDD-CUP 99 using several performance metrics.…”
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  11. 11
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…It has been shown that changing the data width or bit values in the VHDL source code of the subsystem can easily change the subsystems' sizes. …”
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