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  1. 1
    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm

    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm by Fatin Nurjannah, Salauddin

    Published 2018
    “…The techniques is in the Neural Network which has a few popular techniques such as K-Nearest Neighbour Fuzzy Min Max, general Reflex Fuzzy Min Max to get some idea of methodologies, algorithm, techniques and concept of the whole existing project and research study. …”
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  2. 2
    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations.

    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations. by Naghshbandi, Danial, Subramaniam, Shamala, Moghadam, Saeed Rahimi

    Published 2013
    “…This research has focused at developing a discrete-event simulator to implement bandwidth allocation algorithms for a WiMAX base station.The highest urgency first algorithm has been utilized as a benchmark deployment algorithm in order to provide: dynamic downlink/uplink adjustment and latency guarantee for real-time applications. …”
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  3. 3
    Maximum 2-satisfiability in radial basis function neural network

    Maximum 2-satisfiability in radial basis function neural network by Shehab Abdulhabib Alzaeemi, Saratha Sathasivam, Mohd Shareduwan Mohd Kasihmuddin, Mohd. Asyraf Mansor

    Published 2020
    “…MAX2SAT is a case of MAX-kSAT and is written in Conjunctive Normal Form (CNF) with two variables in each clause. …”
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  4. 4
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
    “…After signal management the channels need to be split into sixteen antenna array elements by a means of FPGA board. To do so, the verilog code is written for programming the FPGA base on the signal which is come from DSP. …”
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  5. 5
    Designing and Developing an Intelligent Congkak

    Designing and Developing an Intelligent Congkak by Muhammad Safwan, Mohd Shahidan

    Published 2011
    “…and “Can Min-Max algorithm (MM) be speeded up by using NN as a forward-pruning method?”. …”
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  6. 6
    Fair energy-efficient resource allocation for downlink NOMA heterogeneous networks

    Fair energy-efficient resource allocation for downlink NOMA heterogeneous networks by Ali, Zuhura Juma, Noordin, Nor Kamariah, Sali, Aduwati, Hashim, Fazirulhisyam

    Published 2020
    “…The mathematical formulation of the max-min energy efficiency is a non-convex fractional programming problem and is intractable. …”
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  7. 7
    The implications for ahybrid detection technique against malicious sqlattacks on web applications

    The implications for ahybrid detection technique against malicious sqlattacks on web applications by Bahjat Arif, Sarajaldeen Akram, Wani, Sharyar

    Published 2025
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  8. 8
    Building customer churn prediction models in Indonesian telecommunication company using decision tree algorithm

    Building customer churn prediction models in Indonesian telecommunication company using decision tree algorithm by Ramadhanti,, Darin, Larasati, Aisyah, Muid, Abdul, Mohamad, Effendi

    Published 2023
    “…Based on the results, the company is suggested to promote a retention program based in order to decrease customer churn rate.…”
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  9. 9
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  10. 10
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  11. 11
    Digital Quran With Storage Optimization Through Duplication Handling And Compressed Sparse Matrix Method

    Digital Quran With Storage Optimization Through Duplication Handling And Compressed Sparse Matrix Method by Ashraf Saleh Mohammad Alomoush

    Published 2024
    thesis::doctoral thesis
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  12. 12
    SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment

    SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment by Murad, Saydul Akbar, Zafril Rizal, M. Azmi, Muzahid, Abu Jafar Md, Bhuiyan, Md Khairul Bashar, Saib, Md, Rahimi, Nick, Prottasha, Nusrat Jahan, Bairagi, Anupam Kumar

    Published 2024
    “…Firstly, a Priority-Based Fair Scheduling (PBFS) algorithm has been introduced to schedule jobs so that jobs can access the required resources at optimal times. …”
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  13. 13
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…VHDL can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. …”
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  14. 14
    Fast fourier transform processor implementation for high inputs on field programmable gates array

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. …”
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  15. 15
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. …”
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