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Final exam question paper data encryption and decryption using advance encryption standard / Khairul Nashran Nazari by Nazari, Khairul Nashran

“…A 128-bit key requires 10 rounds where 192-bit and 256-bit requires 12 and 14 rounds respectively. …”
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Optimization of Digital Electronic Circuit Structure Design Using Genetic Algorithm by Chong, Kok Hen

“…GALI is programmed by the success chromosome bits obtained from the simulation phase. …”
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Security analysis of blowfish algorithm by Alabaichi, Ashwak Mahmood, Ahmad, Faudziah, Mahmod, Ramlan

“…Blowfish algorithm (BA) is a symmetric block cipher with a 64-bit block size and variable key lengths from 32 bits up to a maximum of 448 bits. …”
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Encryption using FPGA by Nor Robaini, Ibrahim

“…The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits, this project implements the 128 bit standard on a Field Programming Gate Array (FPGA) using the VHDL, a hardware description language.…”
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Security analysis of blowfish algorithm by Al-Abiachi, Ashwak M., Ahmad, Faudziah, Mahmod, Ramlan

“…Blowfish algorithm (BA) is a symmetric block cipher with a 64-bit block size and variable key lengths from 32 bits up to a maximum of 448 bits.In order to measure the degree of security of blowfish algorithm, some cryptographic tests must be applied such as randomness test, avalanche criteria and correlation coefficient.In this paper we attempt to analyze the security of blowfish using avalanche criteria and correlation coefficient.We analyzed the randomness of the Blowfish output in an earlier paper titled “Randomness Analysis on Blowfish Block Cipher using ECB and CBC Modes”. …”
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Implementation of AES algorithm into information investigation autopsy (IIA) / Ahmad Wafiy Hamad Zaki by Hamad Zaki, Ahmad Wafiy Hamad Zaki

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Parallelization of speech compression based algorithm based on human auditory system on multicore system by Gunawan, Teddy Surya, Kartiwi, Mira, Khalifa, Othman Omran

“…To achieve a scalable parallel speech coding algorithm, single program multiple data (SPMD) programming model was used, in which a single program was written for all cores. …”
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Design and implementation of real data fast fourier transform processor on field programmable gates array by Ahmed, Mohammed Kassim

“…The radix-4 FFT algorithm will be implemented for 64 and 256 points using both 8-bit and 16-bit input width. …”
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An improved RSA cryptosystem based on thread and CRT / Saheed Yakub Kayode and Gbolagade Kazeem Alagbe by Yakub Kayode, Saheed, Kazeem Alagbe, Gbolagade

“…Also, in our method, the key size is extended from 1024 bits to 2048 bits in length to provide a good level of security, since 1024 bits key size is no more appropraiate for protecting data. …”
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OPTIMIZATION OF TWO FISH ENCRYPTION ALGORITHM ON FPGA by DORE RAJA, ANAND A RAJA

“…Besides that, Twofish also uses a 32 bit Pseudo Hadamard Transform to mix the outputs from its 2 parallel 32-bit g functions. …”
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Data Hiding Techniques In Digital Images by Al Thloothi, Salah Ramadan

“…In this side, two programs had been implemented using MATLAB program to illustrate the main idea involved in least significant technique (low bit encoding), and the other to illustrate the masking technique inside the carrier image. …”
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A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors by Lee, Weng Fook

“…One method is to increase the bit size of the microprocessor to 128/256/512 bits. …”
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Booth’s Algorithm Design Using Field Programmable Gate Array by Ab Hadi, Nik Azran, A Aziz, Khairul Azha, Hashim, Nik Mohd Zarifie, Omar, Muhammad Shukri, Jaafar, Anuar

“…The high speed operation and less space and energy required had made the digital devices more preferred.This project is to design digital system which performed fixed point Booth Multiplier Algorithm where the design system would be developed using hardware description language (HDL),in this case,VHDL (VHSIC Hardware Description Language),VHSIC stands for Very High Speed Integrated Circuit.In this project would be used Xilinx ISE 10.1which is the software used to designed digital system for Xilinx manufactured FPGA board.In Xilinx have two main languages which are VHDL and Verilog.For design Booth’s Multiplier Algorithm we used Verilog code which is has to create the program module and test bench.In that case,to design digital system will have input and output which is input is 8 bits and output is 16 bits.Finally, it is proven that the system created can calculate and yield a fixed point multiplied output of the input value. …”
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Logic Algorithm for contour following task: An evaluation using Adept SCARA Robot by Anton, S P, Samsi , Md. Said, M.A., Burhanuddin

“…This paper presents the performance evaluation of logic algorithms for contourfollowing task in order to automate the manual programming process. …”
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Optimization Of Twofish Encryption Algorithm On FPGA by Raja, Ananda Raja Dore, Zain Ali, Noohul Basheer, Hussin, Fawnizu Azmadi

“…Besides that, Twofish also uses a 32 bit Pseudo Hadamard Transform to mix the outputs from its 2 parallel 32-bit g functions. …”
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The implications for ahybrid detection technique against malicious sqlattacks on web applications by Bahjat Arif, Sarajaldeen Akram, Wani, Sharyar

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Error correction for CDMA code in mobile communication by Tiong S.K., Tan C.H., Ding J., Ismail M.

“…A simulation program is developed to study the performance of error correction by studying the BER of the received information bits. � 2003 IEEE.…”

Hardware Acceleration of Window Big-Digit (Wbd) Multiplication for Embedded Applications by Lim, Ee Wah

“…The accelerator is equipped with AXI interface and integrated into an ARM-based SoC system for benchmarking purpose. The test programs are The hardware-accelerated 256-bits multiplication is found that to be 340 fold faster than pure software implementation of classical multiplication. …”
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Security mechanism for wireless Mobile Ad Hoc Networks (MANET) by Abdul Rahman Sidek, Diana

“…These algorithms are chosen because they are suitable for low bit rate data. …”
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Optimized fast fourier transform architecture using instruction set architecture extension in low-end digital signal controller by Salim, Sani Irwan

“…Compared to the initial processor architecture, the support of extended ISA has increased the UTeMRISC core by 21.8% but at the same time allows to execute Fast Fourier Transform algorithm up to 5× faster. The combine effort of ISA extension and optimized instruction set generation results in up to 1 Mega sample per second, which translated to 66.8% increase of data throughput in the FFT algorithm when compared to a 32-bit architecture. …”
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