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  1. 1
    Final exam question paper data encryption and decryption using advance encryption standard / Khairul Nashran Nazari

    Final exam question paper data encryption and decryption using advance encryption standard / Khairul Nashran Nazari by Nazari, Khairul Nashran

    Published 2017
    “…A 128-bit key requires 10 rounds where 192-bit and 256-bit requires 12 and 14 rounds respectively. …”
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  2. 2
    Parallelization of speech compression based algorithm based on human auditory system on multicore system

    Parallelization of speech compression based algorithm based on human auditory system on multicore system by Gunawan, Teddy Surya, Kartiwi, Mira, Khalifa, Othman Omran

    Published 2012
    “…To achieve a scalable parallel speech coding algorithm, single program multiple data (SPMD) programming model was used, in which a single program was written for all cores. …”
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  3. 3
    Design and implementation of real data fast fourier transform processor on field programmable gates array

    Design and implementation of real data fast fourier transform processor on field programmable gates array by Ahmed, Mohammed Kassim

    Published 2015
    “…The radix-4 FFT algorithm will be implemented for 64 and 256 points using both 8-bit and 16-bit input width. …”
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  4. 4
    OPTIMIZATION OF TWO FISH ENCRYPTION ALGORITHM ON FPGA

    OPTIMIZATION OF TWO FISH ENCRYPTION ALGORITHM ON FPGA by DORE RAJA, ANAND A RAJA

    Published 2004
    “…Twofish uses 4 different, bijective, key-dependent, 8-by-8 bit Sboxes. Twofish uses a single 4 by 4 MDS matrix over GF (28).This is one of the 2 main diffusion elements of Two fish. …”
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    Final Year Project
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  5. 5
    A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors

    A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors by Lee, Weng Fook

    Published 2008
    “…Second is the proof of concept that a large bit size VLIW microprocessor is possible by implementing a 64/128/256 bits data size on an Altera Stratix 2 EP2S180F1508I4 FPGA.…”
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  6. 6
    Optimization Of Twofish Encryption Algorithm On FPGA

    Optimization Of Twofish Encryption Algorithm On FPGA by Raja, Ananda Raja Dore, Zain Ali, Noohul Basheer, Hussin, Fawnizu Azmadi

    Published 2005
    “…Twofish uses 4 different, bijective, key-dependent, 8-by-8 bit Sboxes. Twofish uses a single 4 by 4 MDS matrix over GF (28).This is one of the 2 main diffusion elements of Two fish. …”
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    Conference or Workshop Item
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  7. 7
    Booth’s Algorithm Design Using Field Programmable Gate Array

    Booth’s Algorithm Design Using Field Programmable Gate Array by Ab Hadi, Nik Azran, A Aziz, Khairul Azha, Hashim, Nik Mohd Zarifie, Omar, Muhammad Shukri, Jaafar, Anuar

    Published 2014
    “…The high speed operation and less space and energy required had made the digital devices more preferred.This project is to design digital system which performed fixed point Booth Multiplier Algorithm where the design system would be developed using hardware description language (HDL),in this case,VHDL (VHSIC Hardware Description Language),VHSIC stands for Very High Speed Integrated Circuit.In this project would be used Xilinx ISE 10.1which is the software used to designed digital system for Xilinx manufactured FPGA board.In Xilinx have two main languages which are VHDL and Verilog.For design Booth’s Multiplier Algorithm we used Verilog code which is has to create the program module and test bench.In that case,to design digital system will have input and output which is input is 8 bits and output is 16 bits.Finally, it is proven that the system created can calculate and yield a fixed point multiplied output of the input value. …”
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  8. 8
    Data Hiding Techniques In Digital Images

    Data Hiding Techniques In Digital Images by Al Thloothi, Salah Ramadan

    Published 2003
    “…In this side, two programs had been implemented using MATLAB program to illustrate the main idea involved in least significant technique (low bit encoding), and the other to illustrate the masking technique inside the carrier image. …”
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  9. 9
    An improved RSA cryptosystem based on thread and CRT / Saheed Yakub Kayode and Gbolagade Kazeem Alagbe

    An improved RSA cryptosystem based on thread and CRT / Saheed Yakub Kayode and Gbolagade Kazeem Alagbe by Yakub Kayode, Saheed, Kazeem Alagbe, Gbolagade

    Published 2017
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  10. 10
    Error correction for CDMA code in mobile communication

    Error correction for CDMA code in mobile communication by Tiong S.K., Tan C.H., Ding J., Ismail M.

    Published 2023
    Conference paper
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  11. 11
    Hardware Acceleration of Window Big-Digit (Wbd) Multiplication for Embedded Applications

    Hardware Acceleration of Window Big-Digit (Wbd) Multiplication for Embedded Applications by Lim, Ee Wah

    Published 2015
    “…Algoritma ini berasaskan sistem penomboran Digit Besar (BD) dan bersasarkan nombor besar yang beribu-ribu bit. Berat Hamming bagi sistem pernomboran wBD hanya n 4:6 berbanding dengan n2 bagi sistem binari, n 3 bagi nombor tanpa bersebelahan (NAF) dan n w+1 bagi NAF tetingkap (wNAF). …”
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  12. 12
    The implications for ahybrid detection technique against malicious sqlattacks on web applications

    The implications for ahybrid detection technique against malicious sqlattacks on web applications by Bahjat Arif, Sarajaldeen Akram, Wani, Sharyar

    Published 2025
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  13. 13
    Optimized fast fourier transform architecture using instruction set architecture extension in low-end digital signal controller

    Optimized fast fourier transform architecture using instruction set architecture extension in low-end digital signal controller by Salim, Sani Irwan

    Published 2018
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  14. 14
    Implementation of PRINCE algorithm in FPGA

    Implementation of PRINCE algorithm in FPGA by Abbas Y.A., Jidin R., Jamil N., Z'aba M.R., Rusli M.E., Tariq B.

    Published 2023
    Conference Paper
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  15. 15
    New universal gate library for synthesizing reversible logic circuit using genetic programming

    New universal gate library for synthesizing reversible logic circuit using genetic programming by Abubakar, M.Y., Jung, L.T., Zakaria, M.N., Younesy, A., Abdel-Atyz, A.-H.

    Published 2016
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  16. 16
    Implementing case-based reasoning approach to framework documentation

    Implementing case-based reasoning approach to framework documentation by Hajar M.J., Lee S.P.

    Published 2023
    Conference paper
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  17. 17
    Speech compression using compressive sensing on a multicore system

    Speech compression using compressive sensing on a multicore system by Gunawan, Teddy Surya, Khalifa, Othman Omran, Shafie, Amir Akramin, Ambikairajah, Eliathamby

    Published 2011
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    Proceeding Paper
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  18. 18
    Secure radio telemetry and data acquisition using wireless data communication system with portable UHF transceivers / Mohd Dani Baba and Deepak Kumar Ghodgaonkar

    Secure radio telemetry and data acquisition using wireless data communication system with portable UHF transceivers / Mohd Dani Baba and Deepak Kumar Ghodgaonkar by Baba, Mohd Dani, Ghodgaonkar, Deepak Kumar

    Published 2003
    “…The data collected at RTS site are encrypted prior to transmission to the BTS by employing the One Time Pad (OTP) and Caesar Cipher algorithms. These algorithms are chosen because they are suitable for low bit rate data. …”
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    Research Reports
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  19. 19
    Performance analysis of digital watermarking on medical images / Syaza ‘Aqilah Zul Wizaratain

    Performance analysis of digital watermarking on medical images / Syaza ‘Aqilah Zul Wizaratain by Zul Wizaratain, Syaza ‘Aqilah

    Published 2020
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  20. 20
    Digital Quran With Storage Optimization Through Duplication Handling And Compressed Sparse Matrix Method

    Digital Quran With Storage Optimization Through Duplication Handling And Compressed Sparse Matrix Method by Ashraf Saleh Mohammad Alomoush

    Published 2024
    thesis::doctoral thesis
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