Search Results - (( program 2 bit algorithm ) OR ( java implementation mining algorithm ))
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Direct approach for mining association rules from structured XML data
Published 2012“…The thesis also provides a two different implementation of the modified FLEX algorithm using a java based parsers and XQuery implementation. …”
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Thesis -
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Study and Implementation of Data Mining in Urban Gardening
Published 2019“…Using the J48 tree algorithm implemented through WEKA API on a Java Servlet, data provided is processed to derive a health index of the plant, with the possible outcomes set to “Good,” “Okay”, or “Bad”. …”
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Scalable approach for mining association rules from structured XML data
Published 2009“…Many techniques have been proposed to tackle the problem of mining XML data we study the various techniques to mine XML data and yet We presented a java based implementation of FLEX algorithm for mining XML data.…”
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Mining association rules from structured XML data
Published 2009“…Many techniques have been proposed to tackle the problem of mining XML data. We study the various techniques to mine XML data and yet We presented a java based implementation of FLEX algorithm for mining XML data.…”
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A web-based implementation of k-means algorithms
Published 2022“…This stinginess of proximity measures in data mining tools is stifling the performance of the algorithm. …”
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Final Year Project / Dissertation / Thesis -
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Image clustering comparison of two color segmentation techniques
Published 2010“…The clustering research is regarding the area of data mining and implementation of the clustering algorithms. …”
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Final exam question paper data encryption and decryption using advance encryption standard / Khairul Nashran Nazari
Published 2017“…A 128-bit key requires 10 rounds where 192-bit and 256-bit requires 12 and 14 rounds respectively. …”
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Features selection for intrusion detection system using hybridize PSO-SVM
Published 2016“…Hybridize Particle Swarm Optimization (PSO) as a searching algorithm and support vector machine (SVM) as a classifier had been implemented to cope with this problem. …”
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Parallelization of speech compression based algorithm based on human auditory system on multicore system
Published 2012“…To achieve a scalable parallel speech coding algorithm, single program multiple data (SPMD) programming model was used, in which a single program was written for all cores. …”
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Design and implementation of real data fast fourier transform processor on field programmable gates array
Published 2015“…The radix-4 FFT algorithm will be implemented for 64 and 256 points using both 8-bit and 16-bit input width. …”
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OPTIMIZATION OF TWO FISH ENCRYPTION ALGORITHM ON FPGA
Published 2004“…Twofish uses 4 different, bijective, key-dependent, 8-by-8 bit Sboxes. Twofish uses a single 4 by 4 MDS matrix over GF (28).This is one of the 2 main diffusion elements of Two fish. …”
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Final Year Project -
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A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors
Published 2008“…Second is the proof of concept that a large bit size VLIW microprocessor is possible by implementing a 64/128/256 bits data size on an Altera Stratix 2 EP2S180F1508I4 FPGA.…”
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Optimization Of Twofish Encryption Algorithm On FPGA
Published 2005“…Twofish uses 4 different, bijective, key-dependent, 8-by-8 bit Sboxes. Twofish uses a single 4 by 4 MDS matrix over GF (28).This is one of the 2 main diffusion elements of Two fish. …”
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Conference or Workshop Item -
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Booth’s Algorithm Design Using Field Programmable Gate Array
Published 2014“…The high speed operation and less space and energy required had made the digital devices more preferred.This project is to design digital system which performed fixed point Booth Multiplier Algorithm where the design system would be developed using hardware description language (HDL),in this case,VHDL (VHSIC Hardware Description Language),VHSIC stands for Very High Speed Integrated Circuit.In this project would be used Xilinx ISE 10.1which is the software used to designed digital system for Xilinx manufactured FPGA board.In Xilinx have two main languages which are VHDL and Verilog.For design Booth’s Multiplier Algorithm we used Verilog code which is has to create the program module and test bench.In that case,to design digital system will have input and output which is input is 8 bits and output is 16 bits.Finally, it is proven that the system created can calculate and yield a fixed point multiplied output of the input value. …”
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Data Hiding Techniques In Digital Images
Published 2003“…In this side, two programs had been implemented using MATLAB program to illustrate the main idea involved in least significant technique (low bit encoding), and the other to illustrate the masking technique inside the carrier image. …”
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Hardware Acceleration of Window Big-Digit (Wbd) Multiplication for Embedded Applications
Published 2015“…Algoritma ini berasaskan sistem penomboran Digit Besar (BD) dan bersasarkan nombor besar yang beribu-ribu bit. Berat Hamming bagi sistem pernomboran wBD hanya n 4:6 berbanding dengan n2 bagi sistem binari, n 3 bagi nombor tanpa bersebelahan (NAF) dan n w+1 bagi NAF tetingkap (wNAF). …”
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