Search Results - (( process verification path algorithm ) OR ( java implications _ algorithm ))

Micro-sequencer based control unit design for a central processing unit by Tan, Chang Hai

“…Register transfer logic (RTL) level design methodology namely top level RTL architecture, RTL control algorithm, data path unit design, RTL control sequence table, microsequencer control unit design, integration of control unit and data path unit, and the functional simulation for the design verification are included in this research.…”
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Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area by Lim , Yen Ruen

“…Cryptographic hash functions are generally the basis of a secure network and used for data integrity verification. Cryptographic hash functions carried out processes such as identity verification, file integrity checking, secure key passing, and source code version control. …”
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Development Of Generative Computer-Aided Process Planning System For Lathe Machining by Zubair, Ahmad Faiz

“…These parameters were then useful for tooling selections and tool-path planning. The results from the automatic feature recognitions show less than 0.02% of error in comparison of algorithm overall delta volume, (ODValg) and the manual calculation ODV, (ODVmanual). …”
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HOOPOE: High performance and efficient anonymous handover authentication protocol for flying out of zone UAVs by Khalid, Haqi, Hashim, Shaiful Jahari, Hashim, Fazirulhisyam, Syed Ahamed, Sharifah Mumtazah, Chaudhary, Muhammad Akmal, Altarturi, Hamza H. M., Saadoon, Muntadher

“…Therefore, this paper presents a high-performance and efficient anonymous handover authentication protocol to secure the drone traveling path. The protocol utilizes the advantages of the AES-RSA algorithm to provide efficient and secure key management and a fast verification and signature generation that speeds up drone authentication. …”
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New optimization feature for the developed open cnc controller based on ISO 6983 and ISO 14649 by Obayes, Noor Hatem

“…However, this system has some limitations, such as tool path optimization. This research aims to minimize tool path airtime during machining of input ISO codes via an ant colony optimization algorithm. …”
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A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors by Lee, Weng Fook

“…To prove the concept that such a large bit size VLIW microprocessor can indeed be implemented, the said VLIW microprocessor of bitsize 64/128/256 is programmed on an Altera Stratix 2 EP2S180F1508I4 FPGA and back annotated for verification. In the TSMC 0.35 micron process implementation of the work, the critical path of the VLIW microprocessor of data bus size 128/256/512 is analyzed with its worst path within the adder of the ALU in the execute stage. …”
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Low power pipelined FFT processor architecture on FPGA by Mohd Hassan, Siti Lailatul, Sulaiman, Nasri, Abdul Halim, Ili Shairah

“…Pipelined FFT processor design on FPGA will speed up the design process and flexibility. This paper provides a survey of three types of pipelined FFT architecture, radix-8, radix-4 single path feedback (R4SDF) and radix-4 single-pasth delay commutator implemented on FPGA. …”
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Fingerprint frontier: the evolution of biometric security by Khalifa, Othman Omran

“…Chapter two provides a detailed lens into the core mechanics, followed by an exploration of the algorithms that drive the matching processes in Chapter Three. …”
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The implications for ahybrid detection technique against malicious sqlattacks on web applications by Bahjat Arif, Sarajaldeen Akram, Wani, Sharyar

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Digital forensic investigation reduction model (DIFReM) for Windows 10 OS by Shayau, Yazid Haruna

“…We believe this reduction model with its tool geared towards Microsoft Windows 10 Professional operating system is a more efficient forensic tool for windows 10 64-bit professional than generic tools used and will open a path for OS-defined Forensic tools which will definitely be a delight to many investigators as it will hasten the examination phase of digital forensic process.…”
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Digital Quran With Storage Optimization Through Duplication Handling And Compressed Sparse Matrix Method by Ashraf Saleh Mohammad Alomoush