Search Results - (( parallel implementation path algorithm ) OR ( java application matching algorithm ))

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    Solving traveling salesman problem on cluster compute nodes by I.A., Aziz, Haron, N., Mehat, M., Jung, L.T., Mustapa, A.N., Akir, E.A.P.

    Published 2009
    “…In this paper, we present a parallel implementation of a solution for the Traveling Salesman Problem (TSP). …”
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    Article
  3. 3

    High-Speed shortest path co-processor design by Idris, Mohd Yamani Idna, Abu Bakar, Suraya, Tamil, Emran Mohd, Razak, Zaidi, Noor, Noorzaily Mohamed

    Published 2009
    “…Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. …”
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    Development of an automatics parallel parking system for nonholonomic mobile robot by Mohd Fairuz , Abdollah, Syed Najib , Syed Salim, Irma Wani , Jamaludin, Muhammad Nizam , Kamarudin

    Published 2011
    “…The configuration of the system consists of ultrasonic sensor, rotary encoder, controller, and actuators. The path planning algorithm is developed based on the data acquired from the sensor. …”
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    OPTIMAL DATAPATH DESIGN FOR A CRYPTOGRAPHIC PROCESSOR: THE BLOWFISH ALGORITHM by Zain Ali, Noohul Basheer, Noras, James

    Published 2001
    “…An 8-bit parallel data-path gives the best performance, mapping into 4 independent 8-bit modules, with a throughput at least 4 times greater than with 32-bit hardware. …”
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    A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors by Lee, Weng Fook

    Published 2008
    “…An adder algorithm using repetitive constructs in a parallel algorithm that allows for efficient and optimal synthesis for large data bus size is proposed as a suitable implementation for the adder within the ALU. …”
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    Thesis
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    A test case generation framework based on UML statechart diagram by Salman, Yasir Dawood

    Published 2018
    “…Current studies also hardly address loops and parallel paths issues, and achieved low coverage criteria. …”
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    A new parameterized architectural design for SENSE reconstruction by Siddiqui, M.F., Reza, A.W., Kanesan, J., Omer, H.

    Published 2014
    “…Complex multiplier, divider and complex matrix multiplier modules are designed to implement the algorithm. Furthermore, the variable data bus widths are used in the data path of the architecture, which leads to reduce the hardware cost and silicon area. …”
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    Restoration planning strategy of transmission system based on optimal energizing time of sectionalizing islands / Dian Najihah Abu Talib by Dian Najihah , Abu Talib

    Published 2019
    “…Parallel processing is implemented together with the proposed strategy to minimize the program running time. …”
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    Securing cloud data system (SCDS) for key exposure using AES algorithm by Thabet Albatol, Mohammed Samer Hasan

    Published 2021
    “…The AES algorithm has its own structure to encrypt and decrypt sensitive data that make the attackers difficult to get the real data when encrypting by AES algorithm. …”
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    Detection of black hole nodes in mobile ad hoc network using hybrid trustworthiness and energy consumption techniques by Mustafa, Ahmed Sudad

    Published 2017
    “…In this thesis, a hybrid detection algorithm mechanism has been proposed which combines two detection algorithms based on nodes’ trustworthiness and energy consumption in a parallel manner in order to detect the black hole nodes. …”
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    Thesis
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    Magnetic resonance imaging sense reconstruction system using FPGA / Muhammad Faisal Siddiqui by Muhammad Faisal , Siddiqui

    Published 2016
    “…Parallel imaging is a robust method for accelerating the data acquisition in Magnetic Resonance Imaging (MRI). …”
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  17. 17

    Online teleoperation of writing manipulator through graphics processing unit based accelerated stereo vision by Abu Raid, Fadi Imad Osman

    Published 2021
    “…These algorithms are then parallelized using Compute Unified Device Architecture CUDA C language to run on Graphics Processing Unit GPU for hardware acceleration. …”
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