Search Results - (( parallel implementation modified algorithm ) OR ( parallel optimization path algorithm ))

Parallel implementation of genomic sequences classification using modified gabor wavelet transform on multicore systems by Gunawan, Teddy Surya, Ambikairajah, Eliathamby

“…Single Program Multiple Data (SPMD) parallel paradigm will be used in the parallel implementation. …”
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Tool path generation of contour parallel based on ant colony optimisation by Abdullah, Haslina, Ramli, Rizauddin, Abd Wahab, Dzuraidah, Abu Qudeiri, Jaber

“…An Ant Colony Optimisation (ACO) method is used to optimize the tool path length because of its capability to find the shortest tool path length. …”
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Parallel algorithms for numerical simulations of EHD ion-drag micropump on distributed parallel computing systems by Shakeel Ahmed, Kamboh

“…A data parallel algorithm (DPA-EHD) is designed and implemented for the EHD equations. …”
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Minimizing machining airtime motion with an ant colony algorithm by Abdullah, Haslina, Ramli, Rizauddin, Abd Wahab, Dzuraidah, Abu Qudeiri, Jaber

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Parallel implementation of genomic sequences classification using modified Gabor wavelet transform on multicore systems by Gunawan, Teddy Surya, Ambikairajah, Eliathamby

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Parallel Implementation of Two Level Barotropic Models Applied to the Weather Prediction Problem by Bahri, Susila

“…To process the data collected from British Atmospheric Data Centre (BADC), the sequential programs in row and columnwise fashions are developed and implemented. Then the parallel algorithms are constructed and run using the Beowulf Cluster machine. …”
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OPTIMAL DATAPATH DESIGN FOR A CRYPTOGRAPHIC PROCESSOR: THE BLOWFISH ALGORITHM by Zain Ali, Noohul Basheer, Noras, James

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Parallel Diagonally Implicit Runge-Kutta Methods For Solving Ordinary Differential Equations by Din, Ummul Khair Salma

“…All algorithms are written in C language and the parallel code is implemented on Sun Fire V1280 distributed memory system. …”
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A modified approach to improve the performance of AES using feistel structure by Al-Ansi, Afeef Yahya Ahmed

“…The method support parallel implementation with little overhead.…”
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Resource Minimization in a Real-time Depth-map Processing System on FPGA by Ngo, Huy Tan, Hamid, Nor Hisham, Sebastian , Patrick, Yap, Vooi Voon

“…Depth-map algorithm allows camera system to estimate depth. It is a computational intensive algorithm, but can be implemented with high speed on hardware due to the parallelism property. …”
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Restoration planning strategy of transmission system based on optimal energizing time of sectionalizing islands / Dian Najihah Abu Talib by Dian Najihah , Abu Talib

“…There are two discrete optimization techniques used in this work, which are the Artificial Bee Colony algorithm and Evolutionary Programming. …”
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MINIMIZATION OF RESOURCE UTILIZATION FOR A REAL-TIME DEPTH-MAP COMPUTATIONAL MODULE ON FPGA by NGO , NGO HUY TAN

“…However, the issue can also be addressed by implementing hardware architectures without the need to modify the depth-map algorithm. …”
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Development of a real-time clutch transition strategy for a parallel hybrid electric vehicle by Vu, Trieu Minh

“…Model predictive control (MPC) has been used for this model and tested with different control horizons and weighting factors to verify the ability of MPC to control the vehicle speeds for the clutch engagement. Some modified MPC algorithms with softened constraints and with output regions have been also studied to improve the robustness and the ability of this controller. …”
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Process Planning Optimization In Reconfigurable Manufacturing Systems by Musharavati, Farayi

“…The five (5) AADTs include; a variant of the simulated annealing algorithm that implements heuristic knowledge at critical decision points, two (2) cooperative search schemes based on a “loose hybridization” of the Boltzmann Machine algorithm with (i) simulated annealing, and (ii) genetic algorithm search techniques, and two (2) modified genetic algorithms. …”
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Automatic generic process migration system in linux by Zarrabi, Amirreza

“…A migration algorithm is designed which attempts to exploit the unique features of the basic migration algorithms to form a generic algorithm. …”
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Review of the grey wolf optimization algorithm: variants and applications by Liu, Yunyun, As’arry, Azizan, Hassan, Mohd Khair, Hairuddin, Abdul Aziz

“…It then lays out the theoretical foundation and key procedures involved in the GWO, following which it comprehensively examines the most recent iterations of the algorithm and categorizes them into parallel, modified, and hybridized variations. …”
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OPTIMIZATION OF TWO FISH ENCRYPTION ALGORITHM ON FPGA by DORE RAJA, ANAND A RAJA

“…For this project, 2 different optimized designs were implemented. The first design (Design I) was implemented with minimum hardware resources usage, using a single F -Function (modified) and was optimized with reasonable latency, throughput and throughput per gate. …”
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Dual search maximum power point algorithm based on mathematical analysis under partially-shaded conditions by Hajighorbani, Shahrooz

“…The significant reduction of oscillation in power is observed to be due to implementation of the modified P&O.As a conclusion, the DSMPP algorithm has successfully been performed to detect the GMPP under PSCs in minimum time, with low oscillation in power, and high accuracy as detecting the GMPP for different scenarios of shadowing.…”
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A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors by Lee, Weng Fook

“…Different adder architectures are investigated for suitability on synthesis implementation of large data bus size adder for efficient usage within the ALU. An adder algorithm using repetitive constructs in a parallel algorithm that allows for efficient and optimal synthesis for large data bus size is proposed as a suitable implementation for the adder within the ALU. …”
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Optimization Of Twofish Encryption Algorithm On FPGA by Raja, Ananda Raja Dore, Zain Ali, Noohul Basheer, Hussin, Fawnizu Azmadi

“…For this project, 2 different optimized designs were implemented. The first design (Design I) was implemented with minimum hardware resources usage, using a single F -Function (modified) and was optimized with reasonable latency, throughput and throughput per gate. …”
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