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  1. 1
    Image clustering comparison of two color segmentation techniques

    Image clustering comparison of two color segmentation techniques by Subramaniam, Kavitha Pichaiyan

    Published 2010
    “…Finally, the algorithm found, which would solve the image segmentation problem.…”
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  2. 2
    Automatic Number Plate Recognition on android platform: With some Java code excerpts

    Automatic Number Plate Recognition on android platform: With some Java code excerpts by ., Abdul Mutholib, Gunawan, Teddy Surya, Kartiwi, Mira

    Published 2016
    “…On the other hand, the traditional algorithm using template matching only obtained 83.65% recognition rate with 0.97 second processing time. …”
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  3. 3
    Development of seven segment display recognition using TensorFlow on Raspberry Pi

    Development of seven segment display recognition using TensorFlow on Raspberry Pi by Gunawan, Teddy Surya, Mohammad Reduwan, Haque, Yaacob, Mashkuri, Mohamed Azmin, Nor Fadhillah, Ismail, Nanang, Ismail, Md Yusof, Kartiwi, Mira, A. Rahman, Azhar

    Published 2022
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  4. 4
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…This kit contains everything that is needed to create a complete system-on-a-programmable-chip (SOPC) solution. …”
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    Learning Object
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  5. 5
    RISC-V instruction set extension on blockchain application

    RISC-V instruction set extension on blockchain application by Cheong , Kin Seng

    Published 2024
    “…A RISC-V GNU toolchain was installed for the compilation of the programme. …”
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    Final Year Project / Dissertation / Thesis
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  6. 6
    Booth’s Algorithm Design Using Field Programmable Gate Array

    Booth’s Algorithm Design Using Field Programmable Gate Array by Ab Hadi, Nik Azran, A Aziz, Khairul Azha, Hashim, Nik Mohd Zarifie, Omar, Muhammad Shukri, Jaafar, Anuar

    Published 2014
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  7. 7
    Investigation on the dynamic of computation of semi autonomous evolutionary computation for syntactic optimization of a set of programming codes

    Investigation on the dynamic of computation of semi autonomous evolutionary computation for syntactic optimization of a set of programming codes by Mohammad Sigit Arifianto, Tze, Kenneth Kin Teo, Liau, Chung Fan, Liawas Barukang, Zaturrawiah Ali Omar

    Published 2007
    “…Genetic Algorithm as one of the Evolutionary Computation method improve the execution of parallel programming codes by optimizing the number of processors and the distribution of data. …”
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    Research Report
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  8. 8
    Design Methodology and Analysis of Hash Function based-on Field Programmable Gate Array for Hash-based Message Authentication Code Application

    Design Methodology and Analysis of Hash Function based-on Field Programmable Gate Array for Hash-based Message Authentication Code Application by SHAMSIAH BINTI, SUHAILI

    Published 2025
    “…All these design methodologies aim to confirm the effect of HDL coding style on the performance of hardware algorithms implemented on FPGA. …”
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  9. 9
    Development of low power viterbi decoder on complex programmable logic device platform

    Development of low power viterbi decoder on complex programmable logic device platform by Abu, Mohd Azlan

    Published 2018
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  10. 10
    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design

    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

    Published 2024
    “…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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  11. 11
    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design

    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

    Published 2024
    “…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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  12. 12
    Agent-based extraction algorithm for computational problem solving

    Agent-based extraction algorithm for computational problem solving by Rajabi, Maryam

    Published 2015
    “…Therefore, utilizing the agent-based featured agents for this purpose is a benefit with the aim of helping novice programmers to understand the CPS without knowing the programming language. …”
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  13. 13
    Design of a reconfigurable computing platform

    Design of a reconfigurable computing platform by Papu J.J., See O.H.

    Published 2023
    “…This paper describes a design of a reconfigurable computing platform (RCP) based on the Intel Xeon general purpose processor and the Nallatech BenNUEY-PCI-4E field programmable gate array (FPGA) motherboard. …”
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  14. 14
    Implementation Of FPGA Based Encryption Chip Using VHD - Data Encryption Standard (DES) Algorithm

    Implementation Of FPGA Based Encryption Chip Using VHD - Data Encryption Standard (DES) Algorithm by Lim, Mui Liang

    Published 2006
    “…Cryptography has a long and fascinating history. Traditional Encryption Algorithms are implemented in software base because of the complexities involved in the operations. …”
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    Monograph
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  15. 15
    Reusable data-path architecture for encryption-then-authentication on FPGA

    Reusable data-path architecture for encryption-then-authentication on FPGA by Abbas Y.A., Jidin R., Jamil N., Zaba M.R.

    Published 2023
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  16. 16
    The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model

    The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model by Abu, Mohd Azlan, Harun, Harlisya, Harmin, Mohammad Yazdi, Abdul Wahab, Noor Izzri, Abdul Kadir, Muhd Khairulzaman

    Published 2016
    “…Purpose – This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). …”
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  17. 17
    Compiler-based prefetching algorithm for recursive data structure

    Compiler-based prefetching algorithm for recursive data structure by Anuar, Nurulhaini

    Published 2007
    “…This best algorithm consists of greedy prefetching and prefetch array algorithms. …”
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  18. 18
    Solution For Nonlinear Riccati Equation By Block Method

    Solution For Nonlinear Riccati Equation By Block Method by Rasedee, AFN, Ijam, HM, Sathar, MHA, Ishak, N, Hamzah, SR, Sahrim, M, Ismail I.

    Published 2024
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  19. 19
    Framework of Multi-Microcontroller Evaluation Tool for a use of Academic Environment

    Framework of Multi-Microcontroller Evaluation Tool for a use of Academic Environment by Selvakumar, Raja Saravana Kumar, Kamarul Hawari, Ghazali, Nik Mohd Kamil, Nik Yusof

    Published 2012
    “…The Multiple Microcontroller Evaluation Tool (MicroEVAT) thus consists of a programmer tool, a main board including adapters for a variety of chip packages, and plug-in modules. …”
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  20. 20
    Framework of Designing Multiple Microcontroller Based Applications

    Framework of Designing Multiple Microcontroller Based Applications by Selvakumar, Raja Saravana Kumar, Kamarul Hawari, Ghazali, Nik Mohd Kamil, Nik Yusof

    Published 2011
    “…The Multiple Microcontroller Evaluation Tool (microEVAT) thus consists of a programmer tool, a main board including adapters for a variety of chip packages, and plug-in modules. …”
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