Search Results - (( java segmentation using algorithm ) OR ( program data max algorithm ))

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  1. 1
    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm

    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm by Fatin Nurjannah, Salauddin

    Published 2018
    “…The implementation of Fuzzy Min Max Neural Network technique has been applied using Matlab Programming. …”
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  2. 2
    Image clustering comparison of two color segmentation techniques

    Image clustering comparison of two color segmentation techniques by Subramaniam, Kavitha Pichaiyan

    Published 2010
    “…Finally, the algorithm found, which would solve the image segmentation problem.…”
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  3. 3
    Maximum 2-satisfiability in radial basis function neural network

    Maximum 2-satisfiability in radial basis function neural network by Shehab Abdulhabib Alzaeemi, Saratha Sathasivam, Mohd Shareduwan Mohd Kasihmuddin, Mohd. Asyraf Mansor

    Published 2020
    “…The simulated results suggest that the proposed algorithm is effective in doing MAX2SAT logic programming by analysing the performance by obtaining lower Root Mean Square Error, high ratio of satisfied clauses and lesser CPU time.…”
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  4. 4
    Automatic Number Plate Recognition on android platform: With some Java code excerpts

    Automatic Number Plate Recognition on android platform: With some Java code excerpts by ., Abdul Mutholib, Gunawan, Teddy Surya, Kartiwi, Mira

    Published 2016
    “…On the other hand, the traditional algorithm using template matching only obtained 83.65% recognition rate with 0.97 second processing time. …”
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  5. 5
    Development of seven segment display recognition using TensorFlow on Raspberry Pi

    Development of seven segment display recognition using TensorFlow on Raspberry Pi by Gunawan, Teddy Surya, Mohammad Reduwan, Haque, Yaacob, Mashkuri, Mohamed Azmin, Nor Fadhillah, Ismail, Nanang, Ismail, Md Yusof, Kartiwi, Mira, A. Rahman, Azhar

    Published 2022
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    Proceeding Paper
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  6. 6
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
    “…If this system is implemented successfully, it could significantly improve the performance of wireless systems in terms of data rates, coverage and range. The best near-term application opportunities for smart antennas are wireless local area networks (WLANs), mobile DBS, WiMax, and cellular areas. …”
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  7. 7
    Building customer churn prediction models in Indonesian telecommunication company using decision tree algorithm

    Building customer churn prediction models in Indonesian telecommunication company using decision tree algorithm by Ramadhanti,, Darin, Larasati, Aisyah, Muid, Abdul, Mohamad, Effendi

    Published 2023
    “…Preventive efforts are needed by predicting the value of churn in the future. This study uses data mining techniques with decision tree algorithms to predict customer churn in one of Indonesian Telecommunication companies. …”
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  8. 8
    Fast fourier transform processor implementation for high inputs on field programmable gates array

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. …”
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  9. 9
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…Using, VHDL (Very-High-Speed-Integrated-Circuit Hardware Description Language) as design tool has the advantage in optimizing the pDSP hardware requirement with ease where varying the size of units such as register files (RF), program sequencer (PS), data address generator (DAG), arithmetic logic unit (ALU), multiply-accumulator (MAC) and shifter can be done by changing the data width or bit values. …”
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