Search Results - (( java implication based algorithm ) OR ( integer implementation design algorithms ))
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Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture
Published 2018“…Both radix-2 and radix-4 FNT modules are implemented and a further design of radix-4 FNT module, named radix-4 CTFNT module that is optimized to fit the multiplication algorithm we used is proposed. …”
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Final Year Project / Dissertation / Thesis -
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Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi
Published 2012“…For the hardware architecture design, we choose bit-serial structure for implementing our algorithm to benefit from its advantages. …”
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Thesis -
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Optimizing tree planting areas through integer programming and improved genetic algorithm
Published 2012“…Therefore, a hybrid algorithm through an incorporation of Integer Programming and Improved Genetic Algorithm was proposed for planting lining design. …”
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Thesis -
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Fpga Implementation Of Metaheuristic Optimization Algorithm
Published 2022“…There is a surge of novel metaheuristics proposed recently, however it is uncertain whether they are suitable for FPGA implementation. In addition, there exists a variety of design methodologies to implement metaheuristics upon FPGA which may improve the performance of the implementation. …”
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Undergraduates Project Papers -
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FPGA implementation of variable precision Euclid’s GCD algorithm
Published 2017“…Finally, comparisons with previous designs/implementations illustrate that the proposed coprocessor implementation is faster than many reported state-of-the-art solutions. …”
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Article -
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FPGA implementation of metaheuristic optimization algorithm
Published 2023“…There is a surge of novel metaheuristics proposed recently, however it is uncertain whether they are suitable for FPGA implementation. In addition, there exists a variety of design methodologies to implement metaheuristics upon FPGA which may improve the performance of the implementation. …”
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Article -
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FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck
Published 2012“…In hardware implementation, there are different architectures that can represent the same algorithm into hardware. …”
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Conference or Workshop Item -
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Hardware architecture of OFCE-HS for hardware implementation
Published 2011“…Attempts to implement OFCE-HS into real-time hardware have been performed by researchers. …”
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Conference or Workshop Item -
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The Construction Of Quantum Block Cipher For Grover Algorithm
Published 2018“…Asymmetric cryptographic algorithms which are based on integer factorization or discrete logarithms problems are rendered unsecured against quantum attacks. …”
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Thesis -
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Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results
Published 2015“…The result is rounded to the nearest integer for divisors of 3, 5, 6, 7 and 9. The methodology of this research are involving design specification, high level design using C++, RTL level description using Verilog, functional verification and logic synthesis using two different technology library. …”
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Research Report -
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Key schedule algorithm based on coordinate geometry of a three-dimensional hybrid cube
Published 2019“…Therefore, it can be concluded that the strength and validity of KSAHC algorithm have been enhanced as compared to other algorithms and can serve as the alternative algorithm in designing security systems.…”
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Thesis -
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Development of symbolic algorithms for certain algebraic processes
Published 2007“…The main objective of the study is to design and implement an effective and efficient symbolic algorithm for the general class of dense polynomials, given the rational number defining terms of their basis. …”
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Monograph -
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Development of symbolic algorithms for certain algebraic processes
Published 2007“…The main objective of the study is to design and implement an effective and efficient symbolic algorithm for the general class of dense polynomials, given the rational number defining terms of their basis. …”
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Monograph -
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Hardware Acceleration of Window Big-Digit (Wbd) Multiplication for Embedded Applications
Published 2015“…In this study, the hardware implementation of wBD multiplier is designed using Verilog and prototyped in FPGA platform. …”
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Thesis -
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Key generation technique based on triangular coordinate extraction for hybrid cubes
Published 2017“…The overall security of HC is improved by the rotation of HCs and enhanced the complexity in the design of key schedule algorithm. The brute force and entropy test are applied in experimental results which proved that the proposed technique is suitable for implementing a key generation technique and free from any predicted keys pattern.…”
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A study on the significance of backlash width values to the performance of the MIQP-based design of MPC
Published 2005“…Simulation results via an industrial Fluidized Catalytic Cracking Unit (FCCU) case study are presented to show the significance of precise estimation of the backlash width in ensuring successful implementation of the MIQP-based design of MPC.…”
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Conference or Workshop Item -
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