Search Results - (( java implication based algorithm ) OR ( gate evaluation path algorithm ))

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  1. 1

    Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation by Ismail, Mohd. Izuan

    Published 2006
    “…The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). …”
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    Thesis
  2. 2

    A review on path collisions and resources usage in hybrid optical network on chip (HONoC) by Razali, Rina Azlin, Othman, Mohamed

    Published 2015
    “…The purpose of this paper is to evaluate main problems in HONoC. From the evaluation, three main problems has been identified which are path collisions, low resource usage and high power consumption in HONoC.…”
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    Conference or Workshop Item
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    Flexible window-based scheduling with critical worst case latency evaluations for real time traffic in time sensitive networks by Muftah, Shalghum Khaled

    Published 2022
    “…Also, implementing all GCLs in the selected path based on TT evaluations without considering their impacts on the AVB performance results in improper scheduling designs. …”
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    Thesis
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