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A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
Published 2008Get full text
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A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
Published 2009Get full text
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Nano-scale VLSI clock routing module based on useful-skew tree algorithm
Published 2006“…We implemented Useful-Skew Tree (UST) algorithm which is based on the deferred-merge embedding (DME) paradigm, as the clock layout synthesis engine. …”
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Tree-based contrast subspace mining method
Published 2020Get full text
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Selection, generation and extraction of MCCTree using XMCCTree
Published 2012Get full text
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Optimized routing algorithm for mobile multicast source in Wireless Mesh Networks
Published 2015Get full text
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