Search Results - (( java implementation tree algorithm ) OR ( program programmes max algorithm ))

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  1. 1

    Study and Implementation of Data Mining in Urban Gardening by Mohana, Muniandy, Lee, Eu Vern

    Published 2019
    “…Using the J48 tree algorithm implemented through WEKA API on a Java Servlet, data provided is processed to derive a health index of the plant, with the possible outcomes set to “Good,” “Okay”, or “Bad”. …”
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    Article
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  3. 3

    Adoption of machine learning algorithm for analysing supporters and non supporters feedback on political posts / Ogunfolajin Maruff Tunde by Ogunfolajin Maruff , Tunde

    Published 2022
    “…The method was implemented using Java and the results of the simulation were evaluated using five standard performance metrics: accuracy, AUC, precision, recall, and f-Measure. …”
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    Thesis
  4. 4

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…This kit contains everything that is needed to create a complete system-on-a-programmable-chip (SOPC) solution. Onboard chips are MAX® EPM7128S and FLEX® 10K EPF10K70-240. …”
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    Learning Object
  5. 5

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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    Thesis
  6. 6

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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    Thesis
  7. 7

    Embedded system for indoor guidance parking with Dijkstra’s algorithm and ant colony optimization by Mohammad Ata, Karimeh Ibrahim

    Published 2019
    “…This study proposes a car parking management system which applies Dijkstra’s algorithm, Ant Colony Optimization (ACO) and Binary Search Tree (BST) in structuring a guidance system for indoor parking. …”
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    Thesis
  8. 8

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…Memory-based architecture chosen to use for FFT processors, due to the reduction in the number of butterflies and rotators, as they are reused for different stages of the FFT, were implemented on Cyclone II Field Programmable Gate Arrays (FPGA). Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. …”
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    Thesis
  9. 9

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). …”
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    Thesis