Search Results - (( java implementation phase algorithm ) OR ( program programmes max algorithm ))

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  1. 1
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
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  2. 2
    Web-based clustering tool using fuzzy k-mean algorithm / Ahmad Zuladzlan Zulkifly

    Web-based clustering tool using fuzzy k-mean algorithm / Ahmad Zuladzlan Zulkifly by Zulkifly, Ahmad Zuladzlan

    Published 2019
    “…All the algorithm for the engine has been developed by using Java script language. …”
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  3. 3
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…This kit contains everything that is needed to create a complete system-on-a-programmable-chip (SOPC) solution. Onboard chips are MAX® EPM7128S and FLEX® 10K EPF10K70-240. …”
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  4. 4
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  5. 5
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  6. 6
    Fast fourier transform processor implementation for high inputs on field programmable gates array

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…Memory-based architecture chosen to use for FFT processors, due to the reduction in the number of butterflies and rotators, as they are reused for different stages of the FFT, were implemented on Cyclone II Field Programmable Gate Arrays (FPGA). Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. …”
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  7. 7
    Optimal route checking using genetic algorithm for UiTM's bus services / Tengku Salman Fathi Tengku Jaafar

    Optimal route checking using genetic algorithm for UiTM's bus services / Tengku Salman Fathi Tengku Jaafar by Tengku Jaafar, Tengku Salman Fathi

    Published 2006
    “…Although from human logical thinking, the route can be generated easily but the calculation of checking the route whether it is optimal route or not is difficult and will take long time to be implemented. This research study with the development of the Optimal Route Checking Using Genetic Algorithm system should solve this scenario. …”
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  8. 8
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). …”
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