Search Results - (( java implementation mining algorithm ) OR ( programmes data integration algorithm ))

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  1. 1
    Direct approach for mining association rules from structured XML data

    Direct approach for mining association rules from structured XML data by Abazeed, Ashraf Riad

    Published 2012
    “…The thesis also provides a two different implementation of the modified FLEX algorithm using a java based parsers and XQuery implementation. …”
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  2. 2
    Study and Implementation of Data Mining in Urban Gardening

    Study and Implementation of Data Mining in Urban Gardening by Mohana, Muniandy, Lee, Eu Vern

    Published 2019
    “…Using the J48 tree algorithm implemented through WEKA API on a Java Servlet, data provided is processed to derive a health index of the plant, with the possible outcomes set to “Good,” “Okay”, or “Bad”. …”
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  3. 3
    Scalable approach for mining association rules from structured XML data

    Scalable approach for mining association rules from structured XML data by Abazeed, Ashraf Riad, Mamat, Ali, Sulaiman, Md. Nasir, Ibrahim, Hamidah

    Published 2009
    “…Many techniques have been proposed to tackle the problem of mining XML data we study the various techniques to mine XML data and yet We presented a java based implementation of FLEX algorithm for mining XML data.…”
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  4. 4
    Mining association rules from structured XML data

    Mining association rules from structured XML data by Abazeed, Ashraf Riad, Mamat, Ali, Sulaiman, Md. Nasir, Ibrahim, Hamidah

    Published 2009
    “…Many techniques have been proposed to tackle the problem of mining XML data. We study the various techniques to mine XML data and yet We presented a java based implementation of FLEX algorithm for mining XML data.…”
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  5. 5
    A web-based implementation of k-means algorithms

    A web-based implementation of k-means algorithms by Lee, Quan

    Published 2022
    “…This stinginess of proximity measures in data mining tools is stifling the performance of the algorithm. …”
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  6. 6
    Image clustering comparison of two color segmentation techniques

    Image clustering comparison of two color segmentation techniques by Subramaniam, Kavitha Pichaiyan

    Published 2010
    “…The clustering research is regarding the area of data mining and implementation of the clustering algorithms. …”
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  7. 7
    Features selection for intrusion detection system using hybridize PSO-SVM

    Features selection for intrusion detection system using hybridize PSO-SVM by Tabaan, Alaa Abdulrahman

    Published 2016
    “…Hybridize Particle Swarm Optimization (PSO) as a searching algorithm and support vector machine (SVM) as a classifier had been implemented to cope with this problem. …”
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  8. 8
    Implementation of PRINCE algorithm in FPGA

    Implementation of PRINCE algorithm in FPGA by Abbas Y.A., Jidin R., Jamil N., Z'aba M.R., Rusli M.E., Tariq B.

    Published 2023
    “…Algorithms; Application programs; Cryptography; Field programmable gate arrays (FPGA); Hardware; Hardware security; High speed cameras; Integrated circuit design; Logic Synthesis; Security of data; Throughput; Architectural modeling; Block ciphers; Cryptographic algorithms; Hardware implementations; PRINCE; Software implementation; Very high speed integrated circuits; VHDL; Computer hardware description languages…”
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  9. 9
    Design and implementation of multimedia digital matrix system

    Design and implementation of multimedia digital matrix system by Chui, Yew Leong, Ramli, Abdul Rahman, Perumal, Thinagaran, Sulaiman, Mohd Yusof, Ali, Mohd Liakot

    Published 2005
    “…Besides, the algorithm enables an accurate prediction to the center of data eye with an even number of oversampling clock to data rate ratio. …”
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  10. 10
    Design of Cryptographic Hardware Module Using FPGA

    Design of Cryptographic Hardware Module Using FPGA by Muhammad Imran, Ahmad, Abdul Rahman, Mohd Saad, Mohd Nazrin, Md Isa, Mohd Taufik, Jusoh, Amir Razif Arief, Jamil Abdullah

    Published 2009
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  11. 11
    Improved genetic algorithm for direct current motor high speed controller implemented on field programmable gate array

    Improved genetic algorithm for direct current motor high speed controller implemented on field programmable gate array by Alkhafaji, Falih Salih

    Published 2019
    “…Firstly, to propose an accurate TF for the tested DC motors by designing High Speed Motor Data Acquisition System (HSMDAQS) to collect data in data to be imported into System Identification (Sys Ident). …”
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  12. 12
    Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation

    Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation by Ismail, Mohd. Izuan

    Published 2006
    “…The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). …”
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  13. 13
    Implementation Of FPGA Based Encryption Chip Using VHD - Data Encryption Standard (DES) Algorithm

    Implementation Of FPGA Based Encryption Chip Using VHD - Data Encryption Standard (DES) Algorithm by Lim, Mui Liang

    Published 2006
    “…The hardware based of encryption chip become realizable with Field Programmable Gate Arrays (FPGAs). There are many researchers used Data Encryption Standard (DES) Algorithm to implement in FPGAs. …”
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  14. 14
    Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing

    Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing by Ch'ng, Heng Sun

    Published 2007
    “…Graphs are pervasive data structures in computer science, and algorithms working with them are fundamental to the field. …”
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  15. 15
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
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  16. 16
    VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM

    VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM by Erdogan, S. S., Abdul Rahman, Abdul Wahab, T., H. Hong

    Published 1993
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  17. 17
    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design

    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

    Published 2024
    “…This article analyses a fast implementation of the Hash-based Message Authentication Code (HMAC), which uses its algorithm to ensure the validity and integrity of data to optimise hardware efficiency and design efficacy using the SHA-256 algorithm. …”
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  18. 18
    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design

    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

    Published 2024
    “…This article analyses a fast implementation of the Hash-based Message Authentication Code (HMAC), which uses its algorithm to ensure the validity and integrity of data to optimise hardware efficiency and design efficacy using the SHA-256 algorithm. …”
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  19. 19
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. …”
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  20. 20
    Design of a floating point unit for 32-bit 5 stage pipeline processor

    Design of a floating point unit for 32-bit 5 stage pipeline processor by Low, Wai Hau

    Published 2020
    “…This project is about the design of a Floating Point Unit (FPU), integrate the FPU into RISC32 processor and synthesize the FPU design on Field Programmable Gate Array (FPGA). …”
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