Search Results - (( java implementation matching algorithm ) OR ( programming programmes max algorithm ))

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  1. 1
    Automatic Number Plate Recognition on android platform: With some Java code excerpts

    Automatic Number Plate Recognition on android platform: With some Java code excerpts by ., Abdul Mutholib, Gunawan, Teddy Surya, Kartiwi, Mira

    Published 2016
    “…On the other hand, the traditional algorithm using template matching only obtained 83.65% recognition rate with 0.97 second processing time. …”
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  2. 2
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
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  3. 3
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…This kit contains everything that is needed to create a complete system-on-a-programmable-chip (SOPC) solution. Onboard chips are MAX® EPM7128S and FLEX® 10K EPF10K70-240. …”
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  4. 4
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  5. 5
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  6. 6
    Fast fourier transform processor implementation for high inputs on field programmable gates array

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…Memory-based architecture chosen to use for FFT processors, due to the reduction in the number of butterflies and rotators, as they are reused for different stages of the FFT, were implemented on Cyclone II Field Programmable Gate Arrays (FPGA). Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. …”
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  7. 7
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). …”
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  8. 8
    Multi-floor indoor location estimation system based on wireless local area network

    Multi-floor indoor location estimation system based on wireless local area network by Chua, Tien Han

    Published 2007
    “…During location estimation, current histogram of RSS at unknown location will be compared to the database. The most probable match is selected and returned as estimated location based on Bayesian filtering algorithm. …”
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  9. 9
    An Agent-Based System with Personalization and Intelligent Assistance Services for Facilitating Knowledge Sharing

    An Agent-Based System with Personalization and Intelligent Assistance Services for Facilitating Knowledge Sharing by Mohd Sharef, Nurfadhlina

    Published 2006
    “…KSFaci is embedded in web environment and is implemented using Java Servlet and runs under Apache server. …”
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