Search Results - (( java implementation matching algorithm ) OR ( program implementation max algorithm ))

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  1. 1
    Automatic Number Plate Recognition on android platform: With some Java code excerpts

    Automatic Number Plate Recognition on android platform: With some Java code excerpts by ., Abdul Mutholib, Gunawan, Teddy Surya, Kartiwi, Mira

    Published 2016
    “…On the other hand, the traditional algorithm using template matching only obtained 83.65% recognition rate with 0.97 second processing time. …”
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  2. 2
    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm

    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm by Fatin Nurjannah, Salauddin

    Published 2018
    “…They have been compare for their advantages and disadvantages. The implementation of Fuzzy Min Max Neural Network technique has been applied using Matlab Programming. …”
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  3. 3
    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations.

    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations. by Naghshbandi, Danial, Subramaniam, Shamala, Moghadam, Saeed Rahimi

    Published 2013
    “…This research has focused at developing a discrete-event simulator to implement bandwidth allocation algorithms for a WiMAX base station.The highest urgency first algorithm has been utilized as a benchmark deployment algorithm in order to provide: dynamic downlink/uplink adjustment and latency guarantee for real-time applications. …”
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  4. 4
    Maximum 2-satisfiability in radial basis function neural network

    Maximum 2-satisfiability in radial basis function neural network by Shehab Abdulhabib Alzaeemi, Saratha Sathasivam, Mohd Shareduwan Mohd Kasihmuddin, Mohd. Asyraf Mansor

    Published 2020
    “…The simulated results suggest that the proposed algorithm is effective in doing MAX2SAT logic programming by analysing the performance by obtaining lower Root Mean Square Error, high ratio of satisfied clauses and lesser CPU time.…”
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  5. 5
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
    “…After modeling, the algorithm is implemented in DSP. By using the Hardware- In-Loop facility of DSP, the comparison between hardware implementation and software modeling is performed. …”
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  6. 6
    Designing and Developing an Intelligent Congkak

    Designing and Developing an Intelligent Congkak by Muhammad Safwan, Mohd Shahidan

    Published 2011
    “…and “Can Min-Max algorithm (MM) be speeded up by using NN as a forward-pruning method?”. …”
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  7. 7
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A type of filter is used to improve the distortion in the output waveform. A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  8. 8
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A type of filter is used to improve the distortion in the output waveform. A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  9. 9
    Fast fourier transform processor implementation for high inputs on field programmable gates array

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. …”
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  10. 10
    Multi-floor indoor location estimation system based on wireless local area network

    Multi-floor indoor location estimation system based on wireless local area network by Chua, Tien Han

    Published 2007
    “…During location estimation, current histogram of RSS at unknown location will be compared to the database. The most probable match is selected and returned as estimated location based on Bayesian filtering algorithm. …”
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  11. 11
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…Emergency door car entry system can be implemented using Field Programmable Gate Array (FPGA) board. …”
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  12. 12
    SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment

    SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment by Murad, Saydul Akbar, Zafril Rizal, M. Azmi, Muzahid, Abu Jafar Md, Bhuiyan, Md Khairul Bashar, Saib, Md, Rahimi, Nick, Prottasha, Nusrat Jahan, Bairagi, Anupam Kumar

    Published 2024
    “…To conduct this experiment, we employed the CloudSim simulator, which is implemented using the Java programming language.…”
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  13. 13
    An Agent-Based System with Personalization and Intelligent Assistance Services for Facilitating Knowledge Sharing

    An Agent-Based System with Personalization and Intelligent Assistance Services for Facilitating Knowledge Sharing by Mohd Sharef, Nurfadhlina

    Published 2006
    “…KSFaci is embedded in web environment and is implemented using Java Servlet and runs under Apache server. …”
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  14. 14
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. …”
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