Search Results - (( java implementation graph algorithm ) OR ( program programmes max algorithm ))
Search alternatives:
- implementation graph »
- java implementation »
- program programmes »
- graph algorithm »
- programmes max »
- max algorithm »
-
1
Implementation of locust inspired scheduling algorithm with huge number of servers for energy efficiency in a cloud datacenter
Published 2019“…In the benchmark paper, the result of implementation of LACE algorithm in 400, 600, 800 and 1000 servers were plotted at different graphs. …”
Get full text
Get full text
Thesis -
2
-
3
FPGA Implementation of Emergency Door Car Entry System
Published 2008“…This kit contains everything that is needed to create a complete system-on-a-programmable-chip (SOPC) solution. Onboard chips are MAX® EPM7128S and FLEX® 10K EPF10K70-240. …”
Get full text
Learning Object -
4
CPLD based controller for single phase inverters
Published 2007“…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
Get full text
Get full text
Thesis -
5
CPLD based controller for single phase inverters
Published 2007“…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
Get full text
Get full text
Thesis -
6
Priority and dynamic quantum time algorithms for central processing unit scheduling
Published 2018“…The proposed algorithms (Priority Dynamic Quantum Time and Multi Priority Dynamic Quantum Time Algorithms) are implemented using JAVA programming language and validated using Key Performance Indicators equations. …”
Get full text
Get full text
Thesis -
7
Fast fourier transform processor implementation for high inputs on field programmable gates array
Published 2018“…Memory-based architecture chosen to use for FFT processors, due to the reduction in the number of butterflies and rotators, as they are reused for different stages of the FFT, were implemented on Cyclone II Field Programmable Gate Arrays (FPGA). Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. …”
Get full text
Get full text
Get full text
Thesis -
8
Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture
Published 2001“…Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). …”
Get full text
Get full text
Thesis -
9
Evolutionary cost-cognizant regression test case prioritization for object-oriented programs
Published 2019“…Therefore, this study proposed a cost-cognizant TCP approach for object-oriented software that uses path-based integration testing to identify the possible execution path extracted from the Java System Dependence Graph (JSDG) model of the source code using forward slicing technique. …”
Get full text
Get full text
Thesis
