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  1. 1
    Embedded system for indoor guidance parking with Dijkstra’s algorithm and ant colony optimization

    Embedded system for indoor guidance parking with Dijkstra’s algorithm and ant colony optimization by Mohammad Ata, Karimeh Ibrahim

    Published 2019
    “…This study proposes a car parking management system which applies Dijkstra’s algorithm, Ant Colony Optimization (ACO) and Binary Search Tree (BST) in structuring a guidance system for indoor parking. …”
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  2. 2
    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm

    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm by Fatin Nurjannah, Salauddin

    Published 2018
    “…The implementation of Fuzzy Min Max Neural Network technique has been applied using Matlab Programming. …”
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  3. 3
    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations.

    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations. by Naghshbandi, Danial, Subramaniam, Shamala, Moghadam, Saeed Rahimi

    Published 2013
    “…This research has focused at developing a discrete-event simulator to implement bandwidth allocation algorithms for a WiMAX base station.The highest urgency first algorithm has been utilized as a benchmark deployment algorithm in order to provide: dynamic downlink/uplink adjustment and latency guarantee for real-time applications. …”
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  4. 4
    Maximum 2-satisfiability in radial basis function neural network

    Maximum 2-satisfiability in radial basis function neural network by Shehab Abdulhabib Alzaeemi, Saratha Sathasivam, Mohd Shareduwan Mohd Kasihmuddin, Mohd. Asyraf Mansor

    Published 2020
    “…The simulated results suggest that the proposed algorithm is effective in doing MAX2SAT logic programming by analysing the performance by obtaining lower Root Mean Square Error, high ratio of satisfied clauses and lesser CPU time.…”
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  5. 5
    Fair energy-efficient resource allocation for downlink NOMA heterogeneous networks

    Fair energy-efficient resource allocation for downlink NOMA heterogeneous networks by Ali, Zuhura Juma, Noordin, Nor Kamariah, Sali, Aduwati, Hashim, Fazirulhisyam

    Published 2020
    “…The mathematical formulation of the max-min energy efficiency is a non-convex fractional programming problem and is intractable. …”
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  6. 6
    Designing and Developing an Intelligent Congkak

    Designing and Developing an Intelligent Congkak by Muhammad Safwan, Mohd Shahidan

    Published 2011
    “…and “Can Min-Max algorithm (MM) be speeded up by using NN as a forward-pruning method?”. …”
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  7. 7
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
    “…The best near-term application opportunities for smart antennas are wireless local area networks (WLANs), mobile DBS, WiMax, and cellular areas. The application targeted for this research is WiMax. …”
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  8. 8
    Building customer churn prediction models in Indonesian telecommunication company using decision tree algorithm

    Building customer churn prediction models in Indonesian telecommunication company using decision tree algorithm by Ramadhanti,, Darin, Larasati, Aisyah, Muid, Abdul, Mohamad, Effendi

    Published 2023
    “…Based on the results, the company is suggested to promote a retention program based in order to decrease customer churn rate.…”
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  9. 9
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. The involved software, hardware, and suitable algorithm to implement and generate the PWM are developed in details. …”
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  10. 10
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. The involved software, hardware, and suitable algorithm to implement and generate the PWM are developed in details. …”
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  11. 11
    SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment

    SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment by Murad, Saydul Akbar, Zafril Rizal, M. Azmi, Muzahid, Abu Jafar Md, Bhuiyan, Md Khairul Bashar, Saib, Md, Rahimi, Nick, Prottasha, Nusrat Jahan, Bairagi, Anupam Kumar

    Published 2024
    “…Finally, the performance evaluation demonstrates that the proposed SG-PBFS algorithm outperforms SG-SJF, SG-LJF, SG-FCFS, SG-EDF, and SG-(MAX-MIN) regarding flow time, makespan time, and total tardiness, which conclusively demonstrates its effectiveness. …”
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  12. 12
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…FPGA board is a board that can be programmed using source code to run the application that has been downloaded into it. …”
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  13. 13
    Fast fourier transform processor implementation for high inputs on field programmable gates array

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. …”
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  14. 14
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). …”
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