Search Results - (( java implementation ((rsa algorithm) OR (path algorithm)) ) OR ( using code max algorithm ))

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  1. 1
    RSA Encryption & Decryption using JAVA

    RSA Encryption & Decryption using JAVA by Ramli, Marliyana

    Published 2006
    “…References and theories to support the research of 'RSA Encryption/Decryption using Java' have been disclosed in Literature Review section. …”
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    Final Year Project
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  2. 2
    AUTOMATED MODEL GENERATION OF FSM AND NUSMV MODEL FROM RSA JAVA SOURCE CODE FOR MODEL CHECKING

    AUTOMATED MODEL GENERATION OF FSM AND NUSMV MODEL FROM RSA JAVA SOURCE CODE FOR MODEL CHECKING by SALLEH AL-HUMAIKANI, MOHAMMED ABDULQAWI

    Published 2021
    “…RSA is one of these encryption algorithms that have been implemented in security systems. …”
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    Thesis
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  3. 3
    An improved RSA cryptosystem based on thread and CRT / Saheed Yakub Kayode and Gbolagade Kazeem Alagbe

    An improved RSA cryptosystem based on thread and CRT / Saheed Yakub Kayode and Gbolagade Kazeem Alagbe by Yakub Kayode, Saheed, Kazeem Alagbe, Gbolagade

    Published 2017
    “…Java programming language is used to implement the algorithm. …”
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  4. 4
    Secure Image Steganography Using Encryption Algorithm

    Secure Image Steganography Using Encryption Algorithm by Siti Dhalila, Mohd Satar, Roslinda, Muda, Fatimah, Ghazali, Mustafa, Mamat, Nazirah, Abd Hamid, An, P.K

    Published 2016
    “…A system based on the proposed algorithm will be implemented using Java and it will be more secured due to double-layer of security mechanisms which are RSA and Diffie-Hellman.…”
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  5. 5
    Heavy Transportation Shortest Route using Dijkstra’s algorithm (HETRO) / Nurul Aqilah Ahmad Nezer

    Heavy Transportation Shortest Route using Dijkstra’s algorithm (HETRO) / Nurul Aqilah Ahmad Nezer by Ahmad Nezer, Nurul Aqilah

    Published 2017
    “…The development tools used in developing this project is NetBeans by using Java for the implementation of the coding. The methodology that used for developing this system is the Dijkstra’s algorithm. …”
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  6. 6
    Digitally signed electronic certificate for workshop / Azinuddin Baharum

    Digitally signed electronic certificate for workshop / Azinuddin Baharum by Baharum, Azinuddin

    Published 2017
    “…Digital Signature was encrypted by RSA Algorithm, a very powerful asymmetrical encryption. …”
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  7. 7
    Embedded system for indoor guidance parking with Dijkstra’s algorithm and ant colony optimization

    Embedded system for indoor guidance parking with Dijkstra’s algorithm and ant colony optimization by Mohammad Ata, Karimeh Ibrahim

    Published 2019
    “…BST inserts the nodes in the way that the Dijkstra’s can find the empty parking in fastest way. Dijkstra’s algorithm initials the paths to finding the shortest path while ACO optimizes the paths. …”
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  8. 8
    Path planning for unmanned aerial vehicle (UAV) using rotated accelerated method in static outdoor environment

    Path planning for unmanned aerial vehicle (UAV) using rotated accelerated method in static outdoor environment by Shaliza Hayati A. Wahab, Nordin Saad, Azali Saudi, Ali Chekima

    Published 2021
    “…In this study, a fast iterative method known as Rotated Successive Over-Relaxation (RSOR) is introduced. The algorithm is implemented in a self-developed 2D Java tool, UAV Planner. …”
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  9. 9
    Smart appointment organizer for mobile application / Mohd Syafiq Adam

    Smart appointment organizer for mobile application / Mohd Syafiq Adam by Adam, Mohd Syafiq

    Published 2009
    “…The main component of this prototype is the use of Dijkstra algorithm to compute the shortest path from source of appointment to the 6 points of destinations within UiTM Shah Alam. …”
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  10. 10
    PAPR and BER analysis of mobile WiMAX system using QC-LDPC code with STFBC MIMO OFDMA system / Siti Nor Hasima Mat Jusoh

    PAPR and BER analysis of mobile WiMAX system using QC-LDPC code with STFBC MIMO OFDMA system / Siti Nor Hasima Mat Jusoh by Mat Jusoh, Siti Nor Hasima

    Published 2014
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  11. 11
    WIMAX TESTBED

    WIMAX TESTBED by KOH , MINGHAO

    Published 2008
    “…This project also takes the first few steps of hardware implementation by using Real Time Workshop to convert the Simulink model into C codes which run outside MATLAB. …”
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  12. 12
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
    “…After modeling, the algorithm is implemented in DSP. By using the Hardware- In-Loop facility of DSP, the comparison between hardware implementation and software modeling is performed. …”
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  13. 13
    The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model

    The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model by Abu, Mohd Azlan, Harun, Harlisya, Harmin, Mohammad Yazdi, Abdul Wahab, Noor Izzri, Abdul Kadir, Muhd Khairulzaman

    Published 2016
    “…Design/methodology/approach – The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. …”
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  14. 14
    Dynamic transmit antenna shuffling scheme for hybrid multiple-input multiple-output in layered architecture

    Dynamic transmit antenna shuffling scheme for hybrid multiple-input multiple-output in layered architecture by Chong, Jin Hui

    Published 2010
    “…Finally, the performance of V-BLAST/STBC transceiver scheme with proposed LC-QR algorithm is compared with other MIMO systems, such as V-BLAST and orthogonal space-time block codes. …”
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  15. 15
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…Altera® Quartus II is used to create the source code and download it into the FPGA board. …”
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    Learning Object
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  16. 16
    A multilayered convolutional sparse coding framework for modeling of pooling operation of convolution neural networks

    A multilayered convolutional sparse coding framework for modeling of pooling operation of convolution neural networks by , Abdul Wahid, Khan, Adnan Umar, , Mukhtarullah, Khan, Sheroz, Shah, Jawad

    Published 2019
    “…The multilayered version of CSC(ML-CSC) is shown to be connected to forward pass of CNNs and dictionary learning and sparse coding algorithms of this model are analyzed for solving classification and inverse problems in image processing. …”
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  17. 17
    Fractal coding of bio-metric image for face authentication

    Fractal coding of bio-metric image for face authentication by Ahadullah, Md

    Published 2021
    “…This thesis implements the algorithms for the Methods of CPM, BPBM fractal coding, and its application. …”
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  18. 18
    Design of an OFDM transmitter and receiver using FPGA

    Design of an OFDM transmitter and receiver using FPGA by Loo, Kah Cheng

    Published 2004
    “…This performance of the coding is analyzed from the result of timing simulation using Altera Max Plus II…”
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  19. 19
    Competitive improvement of the time complexity to encode fractal image: by applying symmetric central pixel of the block

    Competitive improvement of the time complexity to encode fractal image: by applying symmetric central pixel of the block by Md Ahadullah, Sapar, Siti Hasana, Al-Saidi, Nadia Mohammed Ghanim, Md Said, Mohamad Rushdan

    Published 2021
    “…As a consequence, the symmetrical CP of odd pixels block, reduction of block space, and edge pixel selection accomplished faster coding and competitive image quality than existing known exhaustive search algorithms.…”
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  20. 20
    Development of low power viterbi decoder on complex programmable logic device platform

    Development of low power viterbi decoder on complex programmable logic device platform by Abu, Mohd Azlan

    Published 2018
    “…Consequently, the number of logic gates and the total power consumption of the STTC Viterbi decoder can be reduced by using the new algorithms. The proposed algorithms have been designed and implemented by using MATLAB, Altera Quartus 2 and Altera MAX V CPLD board. …”
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