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  1. 1
    Optimization of Digital Electronic Circuit Structure Design Using Genetic Algorithm

    Optimization of Digital Electronic Circuit Structure Design Using Genetic Algorithm by Chong, Kok Hen

    Published 2008
    “…The GA process (Inter Loop GA), crossover operator (Fix Multiple Point Crossover), mutation operator (Random Discrete Mask Mutation) and fitness function (Constraint Fitness and Gate Optimization Fitness) were developed in this research. …”
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  2. 2
    The development of RNA logic gates library for the construction of molecular information processing circuits / Lee Yiling

    The development of RNA logic gates library for the construction of molecular information processing circuits / Lee Yiling by Lee , Yiling

    Published 2016
    “…At its core, these devices can process physical or chemical inputs to generate outputs imitating conventional Boolean logical operators. …”
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  3. 3
    Studies on flat CORDIC implementation in field programmable gate arrays (FPGA) / Meera Subramaniam

    Studies on flat CORDIC implementation in field programmable gate arrays (FPGA) / Meera Subramaniam by Meera , Subramaniam

    Published 2004
    “…It is an iterative process of rotations that are carried out through simple shift and addition operations. …”
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  4. 4
    Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264

    Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264 by Fatemi, M.R.H., Ates, H.F., Salleh, R.

    Published 2010
    “…In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. …”
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  5. 5
    Application of the Whale Optimization Algorithm (WOA) in Reservoir Optimization Operation Under Investigation of Climate Change Impact: A Case Study at Klang Gate Dam, Malaysia

    Application of the Whale Optimization Algorithm (WOA) in Reservoir Optimization Operation Under Investigation of Climate Change Impact: A Case Study at Klang Gate Dam, Malaysia by Lai V., Huang Y.F., Koo C.H., Ahmed A.N., El-Shafie A.

    Published 2024
    “…In Malaysia, specifically at the Klang Gate Dam (KGD), very little organized information has been collected in investigating future reservoir operations considering such climate anomalies and complexities. …”
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  6. 6
    Enhancing performance of XTS cryptography mode of operation using parallel design

    Enhancing performance of XTS cryptography mode of operation using parallel design by Ahmed Alomari, Mohammad

    Published 2009
    “…To fully utilize the performance potential of XTS mode of operation, a parallel design for the algorithm is proposed. …”
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  7. 7
    Fast fourier transform processor implementation for high inputs on field programmable gates array

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. …”
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  8. 8
    Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing

    Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing by Ch'ng, Heng Sun

    Published 2007
    “…This thesis proposes a graph processing hardware accelerator for shortest path algorithms applied in nanometer VLSI interconnect routing problems. …”
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  9. 9
    A 2x2 bit multiplier using hybrid 13 t full adder with vedic mathematics method

    A 2x2 bit multiplier using hybrid 13 t full adder with vedic mathematics method by Lee, Shing Jie, Ruslan, Siti Hawa

    Published 2018
    “…The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. …”
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  10. 10
    Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture

    Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture by Chang, Boon Chiao

    Published 2018
    “…While GPU allowed users to configure each of the cores (processing units) to perform independent tasks, FPGA provides users a platform to design the processing units themselves to perform dedicated arithmetic and logic operation.In our GPU implementation, we present two different large integer algorithms implementation on two generation of NVIDIA GPU architectures, Kepler and Pascal. …”
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  11. 11
    BinDCT Design and Implementation on FPGA with Low Power Architecture

    BinDCT Design and Implementation on FPGA with Low Power Architecture by Jabbar, Mohamad Hairol

    Published 2008
    “…As this algorithm uses simple arithmetic operations (shift and add) rather than floating-point multiplications, low power hardware implementation is very promising. …”
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  12. 12
    Design and Implementation of Advanced Encryption Standard Using Verilog HDL

    Design and Implementation of Advanced Encryption Standard Using Verilog HDL by Shamsiah, Suhaili, Rene Brooke, Fredrick, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2020
    “…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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  13. 13
    A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method

    A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method by Lee, Shing Jie, Ruslan, Siti Hawa

    Published 2018
    “…The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. …”
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  14. 14
    Design of field programmable gate array-based proportional-integral-derivative fuzzy logic controller with tunable ganin

    Design of field programmable gate array-based proportional-integral-derivative fuzzy logic controller with tunable ganin by Obaid, Zeyad Assi

    Published 2010
    “…Many of fuzzy control applications require real-time operation; higher density programmable logic devices such as Field Programmable Gate Array (FPGA) can be used to integrate large amounts of logic in a single IC. …”
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  15. 15
    The implications for ahybrid detection technique against malicious sqlattacks on web applications

    The implications for ahybrid detection technique against malicious sqlattacks on web applications by Bahjat Arif, Sarajaldeen Akram, Wani, Sharyar

    Published 2025
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  16. 16
    Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi

    Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi by Hosseiny Fatemi, Mohammad Reza

    Published 2012
    “…Implementation results show that our design can support real-time HD1080 format with 20.3 K gates at the operation frequency of 88.3 MHz.…”
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  17. 17
    Design and implementation of advanced encryption standard using verilog HDL

    Design and implementation of advanced encryption standard using verilog HDL by Shamsiah, Suhaili, Fredrick, Rene Brooke, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2022
    “…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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  18. 18
    Instruction Set Extension Of A Low-End Reconfigurable Microcontroller In Bit-Sorting Implementation

    Instruction Set Extension Of A Low-End Reconfigurable Microcontroller In Bit-Sorting Implementation by Salim, Sani Irwan, Soo, Yew Guan, Samsudin, Sharatul Izah

    Published 2018
    “…It was found that the ISA extension from 12-bit to 16-bit has produced a faster execution time with fewer resource utilization when implementing the bit-sorting algorithm. The overall development process used in this research is flexible enough for further investigation either by extending its module to more complex algorithms or evaluating other designs of its components.…”
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  19. 19
    FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard

    FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard by Shyamsi, M., Ibrahimy, Muhammad Ibn, Motakabber, S. M. A., Ahsan, M. R.

    Published 2015
    “…Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis, etc. …”
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  20. 20
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…Based on the functional verification, the designed pDSP is able to perform mathematical operations required in signal processing. The speed of the operation is dependent on the size of the datapath as well as the type of FPGA chips. …”
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