Search Results - (( gate integration process algorithm ) OR ( java implication based algorithm ))

Optimization of Digital Electronic Circuit Structure Design Using Genetic Algorithm by Chong, Kok Hen

“…The complexity of the digital electronic circuit is due to the number of gates used per system as well as the interconnection of the gates. …”
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Design of Cryptographic Hardware Module Using FPGA by Muhammad Imran, Ahmad, Abdul Rahman, Mohd Saad, Mohd Nazrin, Md Isa, Mohd Taufik, Jusoh, Amir Razif Arief, Jamil Abdullah

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Implementation of PRINCE algorithm in FPGA by Abbas Y.A., Jidin R., Jamil N., Z'aba M.R., Rusli M.E., Tariq B.

Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing by Ch'ng, Heng Sun

“…This thesis proposes a graph processing hardware accelerator for shortest path algorithms applied in nanometer VLSI interconnect routing problems. …”
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OPTIMIZATION OFADVANCEDENCRYPTION STANDARD (AES) IN FPGA IMPLEMENTATION USING S-BOX INTEGRATION by Lee, Yi Lin

“…Hardware complexity is reduced to 69% of its originalwhile still able to function at core process of only 12 cycles.…”
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The development of RNA logic gates library for the construction of molecular information processing circuits / Lee Yiling by Lee , Yiling

“…We designed a library of RNA-YES gates, which can be integrated into an RNA circuit imitating a seven-segment display (SSD). …”
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Design of field programmable gate array-based proportional-integral-derivative fuzzy logic controller with tunable ganin by Obaid, Zeyad Assi

“…Many of fuzzy control applications require real-time operation; higher density programmable logic devices such as Field Programmable Gate Array (FPGA) can be used to integrate large amounts of logic in a single IC. …”
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Design of a reconfigurable computing platform by Papu J.J., See O.H.

“…The PSP also automates the synthesis and implementation process integration to generate the bitstream file from the Xilinx ISE foundation tool. …”

ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor by Jia, Hui Lim, Yuan, Wen Hau, Hoe, Tung Yew, Sreedharan Baskara Dass

“…Moreover, long hour ECG monitoring requires an efficient architecture to support real-time processing and low power consumption. This paper presents an application specific integrated circuit (ASIC) design of Pan-and-Tompkins ECG pre-processing algorithm which aims to remove several unwanted noise to increase analysis accuracy. …”
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VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM by Erdogan, S. S., Abdul Rahman, Abdul Wahab, T., H. Hong

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A step towards the development of VHDL model for ANN based EMG signal classifier by Ahsan, Md. Rezwanul, Ibrahimy, Muhammad Ibn, Khalifa, Othman Omran

“…VHDL (Very High Speed Integrated Circuit Hardware Description Language) has been used to model the algorithm and which can be implemented into the target device FPGA (Field Programmable Gate Array). …”
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VHDL modeling of EMG signal classification using artificial neural network by Ahsan, Md. Rezwanul, Ibrahimy, Muhammad Ibn, Khalifa, Othman Omran, Ullah, Mohammad Habib

“…VHDL (Very High Speed Integrated Circuit Hardware Description Language) has been used to model the algorithm implemented into the target device FPGA (Field Programmable Gate Array). …”
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A 2x2 bit multiplier using hybrid 13 t full adder with vedic mathematics method by Lee, Shing Jie, Ruslan, Siti Hawa

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The implications for ahybrid detection technique against malicious sqlattacks on web applications by Bahjat Arif, Sarajaldeen Akram, Wani, Sharyar

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FPGA implementation of MCPFSK modulation for HF data communication by Fitri Dewi, Jaswar, Ahmad Zuri, Sha’ameri

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Instruction Set Extension Of A Low-End Reconfigurable Microcontroller In Bit-Sorting Implementation by Salim, Sani Irwan, Soo, Yew Guan, Samsudin, Sharatul Izah

“…The modules’ integration is implemented using instruction set architecture (ISA) extension technique and is developed on the Field Programmable Gate Array (FPGA). …”
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A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method by Lee, Shing Jie, Ruslan, Siti Hawa

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Deep learning-based vehicular engine health monitoring system utilising a hybrid convolutional neural network/bidirectional gated recurrent unit by Rahim, Md. Abdur, Rahman, Md Mustafizur, Islam, Md. Shofiqul, Md. Muzahid, Abu Jafar, Rahman, Md. Arafatur, D., Ramasamy

“…Several advanced and hybrid deep learning algorithms were applied to monitor engine health and categorise its status by integrating sensor data with evaluated vulnerability information from an infrastructure vulnerability assessment model. …”
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Secure payment parking system (SPS) with Excel database software / Syed Luqman Putra Syed Putra Zainol Alam by Syed Putra Zainol Alam, Syed Luqman Putra

“…Future recommendations may involve expanding the system to include additional payment options, integrating with smart city infrastructure, and incorporating machine learning algorithms for predictive parking availability.…”
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Accelerating FPGA-surf feature detection module by memory access reduction by Mohd. Yamani Idna, Idris, Nor Bakiah, Abd. Warif, Hamzah, Arof, Noorzaily, Mohamed Noor, Ainuddin Wahid, Abdul Wahab, Zaidi, Razak

“…We also found that the SURF algorithm memory access has redundant repeating pattern that can be reduced. …”
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