Search Results - (( evolution estimation path algorithm ) OR ( program implementation max algorithm ))

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  1. 1
    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm

    A multidimensional data descriptor tool based on fuzzy min max neural network algorithm by Fatin Nurjannah, Salauddin

    Published 2018
    “…They have been compare for their advantages and disadvantages. The implementation of Fuzzy Min Max Neural Network technique has been applied using Matlab Programming. …”
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  2. 2
    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations.

    An event-driven simulation for highest urgency first (HUF) : a latency and modulation aware bandwidth allocation algorithm for WiMAX base stations. by Naghshbandi, Danial, Subramaniam, Shamala, Moghadam, Saeed Rahimi

    Published 2013
    “…This research has focused at developing a discrete-event simulator to implement bandwidth allocation algorithms for a WiMAX base station.The highest urgency first algorithm has been utilized as a benchmark deployment algorithm in order to provide: dynamic downlink/uplink adjustment and latency guarantee for real-time applications. …”
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  3. 3
    Maximum 2-satisfiability in radial basis function neural network

    Maximum 2-satisfiability in radial basis function neural network by Shehab Abdulhabib Alzaeemi, Saratha Sathasivam, Mohd Shareduwan Mohd Kasihmuddin, Mohd. Asyraf Mansor

    Published 2020
    “…The simulated results suggest that the proposed algorithm is effective in doing MAX2SAT logic programming by analysing the performance by obtaining lower Root Mean Square Error, high ratio of satisfied clauses and lesser CPU time.…”
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  4. 4
    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array

    Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

    Published 2008
    “…After modeling, the algorithm is implemented in DSP. By using the Hardware- In-Loop facility of DSP, the comparison between hardware implementation and software modeling is performed. …”
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  5. 5
    Designing and Developing an Intelligent Congkak

    Designing and Developing an Intelligent Congkak by Muhammad Safwan, Mohd Shahidan

    Published 2011
    “…and “Can Min-Max algorithm (MM) be speeded up by using NN as a forward-pruning method?”. …”
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  6. 6
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A type of filter is used to improve the distortion in the output waveform. A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  7. 7
    CPLD based controller for single phase inverters

    CPLD based controller for single phase inverters by Saiman, Suhaimi

    Published 2007
    “…A type of filter is used to improve the distortion in the output waveform. A design and implementation of PWM by using complex programmable logic device (CPLD) from Altera MaxPlus II is constructed and programmed. …”
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  8. 8
    Modeling and multi-objective optimal sizing of standalone photovoltaic system based on evolutionary algorithms

    Modeling and multi-objective optimal sizing of standalone photovoltaic system based on evolutionary algorithms by Ridha, Hussein Mohammed

    Published 2020
    “…Firstly, an improved EM (IEM) algorithm is presented to estimate the five parameters of the single PV-module system. …”
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  9. 9
    Dynamic transmit antenna shuffling scheme for hybrid multiple-input multiple-output in layered architecture

    Dynamic transmit antenna shuffling scheme for hybrid multiple-input multiple-output in layered architecture by Chong, Jin Hui

    Published 2010
    “…It is shown that the computational complexity of proposed FAST-QR detection algorithm is approximately 48 % lower than the conventional QR decomposition detection algorithm. …”
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  10. 10
    Fast fourier transform processor implementation for high inputs on field programmable gates array

    Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

    Published 2018
    “…Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. …”
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  11. 11
    FPGA Implementation of Emergency Door Car Entry System

    FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

    Published 2008
    “…Emergency door car entry system can be implemented using Field Programmable Gate Array (FPGA) board. …”
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    Learning Object
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  12. 12
    SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment

    SG-PBFS : Shortest Gap-Priority Based Fair Scheduling technique for job scheduling in cloud environment by Murad, Saydul Akbar, Zafril Rizal, M. Azmi, Muzahid, Abu Jafar Md, Bhuiyan, Md Khairul Bashar, Saib, Md, Rahimi, Nick, Prottasha, Nusrat Jahan, Bairagi, Anupam Kumar

    Published 2024
    “…To conduct this experiment, we employed the CloudSim simulator, which is implemented using the Java programming language.…”
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  13. 13
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. …”
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