Search Results - (( development programmes drops algorithm ) OR ( java optimization path algorithm ))
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1
Embedded system for indoor guidance parking with Dijkstra’s algorithm and ant colony optimization
Published 2019“…BST inserts the nodes in the way that the Dijkstra’s can find the empty parking in fastest way. Dijkstra’s algorithm initials the paths to finding the shortest path while ACO optimizes the paths. …”
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Thesis -
2
SecPath: Energy efficient path reconstruction in wireless sensor network using iterative smoothing
Published 2019“…This work uses iterative smoothing algorithm to find an alternative path with less distance and energy consumption. …”
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Thesis -
3
Energy efficient path reconstruction in wireless sensor network using iPath
Published 2019“…This work uses iterative boosting algorithm to find an alternative path with less distance and energy consumption. …”
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Article -
4
Visdom: Smart guide robot for visually impaired people
Published 2025“…Core functionalities such as path planning, autonomous movement, voice feedback, and app-to-robot communication have been thoroughly tested and optimized. …”
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Final Year Project / Dissertation / Thesis -
5
Evolutionary cost-cognizant regression test case prioritization for object-oriented programs
Published 2019“…Therefore, this study proposed a cost-cognizant TCP approach for object-oriented software that uses path-based integration testing to identify the possible execution path extracted from the Java System Dependence Graph (JSDG) model of the source code using forward slicing technique. …”
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6
An Efficient Energy Aware Adaptive System-On-Chip Architecture For Real-Time Video Analytics
Published 2016“…A Performance model for Zynq is developed using analytical method and used in hardware/software codesign to facilitate algorithms mapping to hardware. …”
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7
Minimization of torque ripple and flux droop using optimal DTC switching and sector rotation strategy
Published 2022“…MATLAB/Simulink software is used to simulate the proposed strategies while a complete setup system consists of a DS1104 digital signal processor (DSP)-board (to implement the DTC algorithm), Field-programmable Gate Arrays (FPGA) (to implement the blanking circuit), two-level and five-level (CHB) inverter circuit, gate driver circuit, and a 1.1 kW induction motor with 2 kW DC generator as a load is developed for testing and verification purpose. …”
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