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  1. 1
    Implementation of locust inspired scheduling algorithm with huge number of servers for energy efficiency in a cloud datacenter

    Implementation of locust inspired scheduling algorithm with huge number of servers for energy efficiency in a cloud datacenter by Azhar, Nur Huwaina

    Published 2019
    “…In the benchmark paper, the result of implementation of LACE algorithm in 400, 600, 800 and 1000 servers were plotted at different graphs. …”
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  2. 2
    Priority and dynamic quantum time algorithms for central processing unit scheduling

    Priority and dynamic quantum time algorithms for central processing unit scheduling by Mohammed, Maysoon A.

    Published 2018
    “…The proposed algorithms (Priority Dynamic Quantum Time and Multi Priority Dynamic Quantum Time Algorithms) are implemented using JAVA programming language and validated using Key Performance Indicators equations. …”
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  3. 3
    Design and analysis of high performance matrix filling for DNA sequence alignment accelerator using asic design flow: article / Nurzaima Mahmod

    Design and analysis of high performance matrix filling for DNA sequence alignment accelerator using asic design flow: article / Nurzaima Mahmod by Mahmod, Nurzaima

    “…To optimize the performance of the algorithm by exploiting parallelism in the design several techniques have been developed. …”
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  4. 4
    Design and analysis of high performance matrix filling for DNA sequence alignment accelerator using ASIC design flow / Nurzaima Mahmod

    Design and analysis of high performance matrix filling for DNA sequence alignment accelerator using ASIC design flow / Nurzaima Mahmod by Mahmod, Nurzaima

    Published 2010
    “…To optimize the performance of the algorithm by exploiting parallelism in the design several techniques have been developed. …”
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  5. 5
    Hardware And Software Partitioning Using Genetic Algorithm In Image Processing Application

    Hardware And Software Partitioning Using Genetic Algorithm In Image Processing Application by Loo, Fang Hean

    Published 2018
    “…In this project, HW-SW Partitioning is used as a process to map each task of image processing application to be executed either in software (Hard Processor System, HPS) or hardware (Field Programmable Gate Array, FPGA). The framework for HW-SW Partitioning using Genetic Algorithm (GA) is developed in MATLAB. …”
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    Monograph
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  6. 6
    A Malay Chatterbot

    A Malay Chatterbot by Lokman, Aina Fatiha

    Published 2005
    “…The simplicity of AIML makes it easy for non-programmers, especially those who already knowHTML, to get started writing chat robots.…”
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    Final Year Project
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  7. 7
    Design and Implementation of Advanced Encryption Standard Using Verilog HDL

    Design and Implementation of Advanced Encryption Standard Using Verilog HDL by Shamsiah, Suhaili, Rene Brooke, Fredrick, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2020
    “…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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  8. 8
    A cluster analysis of population based cancer registry in Brunei Darussalam : an exploratory study

    A cluster analysis of population based cancer registry in Brunei Darussalam : an exploratory study by Lai, Daphne Teck Ching, Owais A. Malik

    Published 2022
    “…The top three prevalent cancers associated with these subgroups were consistently identified using the three algorithms. Upon comparing the subgroups’ ages during diagnosis, we identify possible screening behaviours of specific subgroups, suggesting for early screening awareness programmes. …”
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  9. 9
    Design and implementation of advanced encryption standard using verilog HDL

    Design and implementation of advanced encryption standard using verilog HDL by Shamsiah, Suhaili, Fredrick, Rene Brooke, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2022
    “…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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    Conference or Workshop Item
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  10. 10
    Evolutionary cost-cognizant regression test case prioritization for object-oriented programs

    Evolutionary cost-cognizant regression test case prioritization for object-oriented programs by Bello, AbdulKarim

    Published 2019
    “…Therefore, this study proposed a cost-cognizant TCP approach for object-oriented software that uses path-based integration testing to identify the possible execution path extracted from the Java System Dependence Graph (JSDG) model of the source code using forward slicing technique. …”
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  11. 11
    Development of low cost 3D scanner (LC3S) using Matlab and FPGA / Abdul Rais Abdul Rahim ...[et al.]

    Development of low cost 3D scanner (LC3S) using Matlab and FPGA / Abdul Rais Abdul Rahim ...[et al.] by Abdul Rahman, Abdul Rais, Abdol Rahman, Mohd Adli, Ramli, Muhammad Azizi, Saparon, Azilah

    Published 2018
    “…Nowadays, three dimensional (3D) scanners are getting more popular with the advancement and development in technology. …”
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  12. 12
    A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

    A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC) by Razali R.A., Othman M.

    Published 2023
    Conference Paper
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  13. 13
    Enhancing obfuscation technique for protecting source code against software reverse engineering

    Enhancing obfuscation technique for protecting source code against software reverse engineering by Mahfoudh, Asma

    Published 2019
    “…There is also a need to develop a tool that contains the three approaches where the developer can customize the protection of the source code.…”
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  14. 14
    Cryptographic protection of block-oriented storage devices using AES-XTS in FPGA

    Cryptographic protection of block-oriented storage devices using AES-XTS in FPGA by Ahmed, Shakil

    Published 2013
    “…Also the parallel AES-XTS encryption and decryption design were used to develop integrated chip of AES-XTS on FPGA. The results show that pipelined implementation has outperformed all other implementations. …”
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