Search Results - (( development programme ep algorithm ) OR ( java application optimisation algorithm ))

Study and Implementation of Data Mining in Urban Gardening by Mohana, Muniandy, Lee, Eu Vern

“…The system is essentially a three-part development, utilising Android, Java Servlets, and Arduino platforms to create an optimised and automated urban-gardening system. …”
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VHDL modeling of EMG signal classification using artificial neural network by Ahsan, Md. Rezwanul, Ibrahimy, Muhammad Ibn, Khalifa, Othman Omran, Ullah, Mohammad Habib

“…VHDL (Very High Speed Integrated Circuit Hardware Description Language) has been used to model the algorithm implemented into the target device FPGA (Field Programmable Gate Array). …”
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A step towards the development of VHDL model for ANN based EMG signal classifier by Ahsan, Md. Rezwanul, Ibrahimy, Muhammad Ibn, Khalifa, Othman Omran

“…VHDL (Very High Speed Integrated Circuit Hardware Description Language) has been used to model the algorithm and which can be implemented into the target device FPGA (Field Programmable Gate Array). …”
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Hardware Implementation Of Rc4a Stream Cipher Algorithm by Al Noman, Abdullah

“…For hardware implementation of the design, an Altera Field Programmable Gate Array (FPGA) device, EP20K200EFC484-2X from APEX family, APEX 20KE, has been used. …”
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Web-based expert system for material selection of natural fiber- reinforced polymer composites by Ahmed Ali, Basheer Ahmed

“…Finally, the developed expert system was deployed over the internet with central interactive interface from the server as a web-based application. As Java is platform independent and easy to be deployed in web based application and accessible through the World Wide Web (www), this expert system can be one stop application for materials selection.…”
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VHDL Modelling of FECG Extraction from the Composite Abdominal ECG using Artificial Intelligence by Hasan, Muhammad Asfarul, Ibrahimy, Muhammad Ibn, Uddin, Md. Jasim, Hussain, Mohammed Sazzad, Reaz, Mamun Ibn

“…The purpose of this paper is to model the developed algorithms on FECG signal extraction using VHDL (very high speed integrated circuit hardware description language) for FPGA (field programmable gate array) implementation from the abdominal ECG signal using neural network approach is to provide efficient and effective ways of separating FECG signal and its nature. …”
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