Search Results - (( development programme encryption algorithm ) OR ( java data optimization algorithm ))*
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Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
Published 2006“…The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). …”
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2
Enhancing performance of XTS cryptography mode of operation using parallel design
Published 2009“…Performance evaluation shows that XTS exhibits faster speed when an RC6 encryption algorithm is used, compared to other encryption algorithms such as AES and Twofish. …”
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3
Design and Implementation of Advanced Encryption Standard Using Verilog HDL
Published 2020“…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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Design and implementation of advanced encryption standard using verilog HDL
Published 2022“…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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Fuzzy modeling using Bat Algorithm optimization for classification
Published 2018“…A Sazonov Engine which is a fuzzy java engine is use to apply Bat Algorithm in the experiment. …”
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Undergraduates Project Papers -
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Attribute reduction based scheduling algorithm with enhanced hybrid genetic algorithm and particle swarm optimization for optimal device selection
Published 2022“…Therefore, in this paper, we proposed Dynamic tasks scheduling algorithm based on attribute reduction with an enhanced hybrid Genetic Algorithm and Particle Swarm Optimization for optimal device selection. …”
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A random search based effective algorithm for pairwise test data generation
Published 2011“…This paper proposes an effective random search based pairwise test data generation algorithm named R2Way to optimize the number of test cases. …”
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Cryptographic protection of block-oriented storage devices using AES-XTS in FPGA
Published 2013“…Also the parallel AES-XTS encryption and decryption design were used to develop integrated chip of AES-XTS on FPGA. …”
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10
Scalable approach for mining association rules from structured XML data
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EasyA: Easy and effective way to generate pairwise test data
Published 2013“…This paper proposes a matrix based calculation for pairwise test data generation algorithm named EasyA to optimize the number of test cases. …”
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An ensemble learning method for spam email detection system based on metaheuristic algorithms
Published 2015“…In the second phase, a classifier ensemble learning model is proposed consisting of separate outputs: (i) To select a relevant subset of original features based on Binary Quantum Gravitational Search Algorithm (QBGSA), (ii) To mine data streams using various data chunks and overcome a failure of single classifiers based on SVM, MLP and K-NN algorithms. …”
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13
Features selection for intrusion detection system using hybridize PSO-SVM
Published 2016“…Hybridize Particle Swarm Optimization (PSO) as a searching algorithm and support vector machine (SVM) as a classifier had been implemented to cope with this problem. …”
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14
Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture
Published 2018“…CPU implementations are becoming less efficient in handling the computation of crypto algorithms. Hence, other contemporary processor architectures such as GPU and FPGA have become popular alternative to speed up the computation in recent years.This dissertation first discusses several existing large integer multiplication algorithms and reviews different methods used to implement thediscussed algorithms done by other researchers in both Graphic Processing Unit (GPU) and Field Programmable Gate Array (FPGA).Compared to GPU, FPGA offered more low level design and development to the implementation. …”
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Final Year Project / Dissertation / Thesis -
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Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design
Published 2024“…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design
Published 2024“…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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Enhancing obfuscation technique for protecting source code against software reverse engineering
Published 2019“…There is also a need to develop a tool that contains the three approaches where the developer can customize the protection of the source code.…”
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19
Smart student timetable planner
Published 2025“…Course data is managed in CSV format, parsed into JSON for fast processing, while sessionStorage and localStorage handle user data within active sessions. …”
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Final Year Project / Dissertation / Thesis -
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Challenges of hidden data in the unused area two within executable files
Published 2009“…Problem statement: The executable files are one of the most important files in operating systems and in most systems designed by developers (programmers/software engineers), and then hiding information in these file is the basic goal for this study, because most users of any system cannot alter or modify the content of these files. …”
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