Search Results - (( development programme encryption algorithm ) OR ( java application design algorithm ))
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Challenges of hidden data in the unused area two within executable files
Published 2009“…Problem statement: The executable files are one of the most important files in operating systems and in most systems designed by developers (programmers/software engineers), and then hiding information in these file is the basic goal for this study, because most users of any system cannot alter or modify the content of these files. …”
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Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
Published 2006“…The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). …”
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Enhancing performance of XTS cryptography mode of operation using parallel design
Published 2009“…Performance evaluation shows that XTS exhibits faster speed when an RC6 encryption algorithm is used, compared to other encryption algorithms such as AES and Twofish. …”
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Design and Implementation of Advanced Encryption Standard Using Verilog HDL
Published 2020“…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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Design and implementation of advanced encryption standard using verilog HDL
Published 2022“…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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RSA Encryption & Decryption using JAVA
Published 2006“…The implementation of this project will be based on Rapid Application Design Methodology (RAD) and will be more focusing on research and finding, ideas and the implementation of the algorithm, and finally running and testing the algorithm. …”
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Provider independent cryptographic tools
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Cryptographic protection of block-oriented storage devices using AES-XTS in FPGA
Published 2013“…Also the parallel AES-XTS encryption and decryption design were used to develop integrated chip of AES-XTS on FPGA. …”
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Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture
Published 2018“…CPU implementations are becoming less efficient in handling the computation of crypto algorithms. Hence, other contemporary processor architectures such as GPU and FPGA have become popular alternative to speed up the computation in recent years.This dissertation first discusses several existing large integer multiplication algorithms and reviews different methods used to implement thediscussed algorithms done by other researchers in both Graphic Processing Unit (GPU) and Field Programmable Gate Array (FPGA).Compared to GPU, FPGA offered more low level design and development to the implementation. …”
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Audio Streaming System Using Real-Time Transport Protocol Based on Java Media Framework
Published 2004“…Java Media Framework library and the RTP protocol for audio transmission were used as development tools.The developed system designed in this thesis together with experimental results proved that the system could be implemented successfully. …”
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Design Of Robot Motion Planning Algorithm For Wall Following Robot
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Monograph -
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Network game (Literati) / Chung Mei Kuen
Published 2003“…The main aspect of this thesis is to produce a networked gaming system, which process players. requested to play the game and enabling users to play the graphical game with people through the network. The algorithm design and implementation method must not only be workable, but also highly efficient in terms of execution speed and response time. …”
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Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design
Published 2024“…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design
Published 2024“…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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SANAsms: Secure short messaging system for secure GSM mobile communication
Published 2008“…The application is designed to satisfy the user friendly interfaces and intent to be used by the end user without having the advanced knowledge in mobile security. …”
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Improving Class Timetabling using Genetic Algorithm
Published 2006“…We have targeted the research on class timetabling problem. Hence, Genetic Algorithm (GA) is used as one of the most popular optimization solutions. …”
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