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  1. 1
    Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation

    Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation by Ismail, Mohd. Izuan

    Published 2006
    “…The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). …”
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  2. 2
    Enhancing performance of XTS cryptography mode of operation using parallel design

    Enhancing performance of XTS cryptography mode of operation using parallel design by Ahmed Alomari, Mohammad

    Published 2009
    “…Performance evaluation shows that XTS exhibits faster speed when an RC6 encryption algorithm is used, compared to other encryption algorithms such as AES and Twofish. …”
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  3. 3
    Design and Implementation of Advanced Encryption Standard Using Verilog HDL

    Design and Implementation of Advanced Encryption Standard Using Verilog HDL by Shamsiah, Suhaili, Rene Brooke, Fredrick, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2020
    “…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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  4. 4
    Design and implementation of advanced encryption standard using verilog HDL

    Design and implementation of advanced encryption standard using verilog HDL by Shamsiah, Suhaili, Fredrick, Rene Brooke, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2022
    “…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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  5. 5
    A performance analysis of association rule mining algorithms

    A performance analysis of association rule mining algorithms by Fageeri, S.O., Ahmad, R., Alhussian, H.

    Published 2016
    “…The results of the CPU profiler of Java VisualVM showed that Binary-Based algorithm performs better than Eclat algorithm in-terms of both execution times and memory usage. …”
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  6. 6
    Implementation of PRINCE algorithm in FPGA

    Implementation of PRINCE algorithm in FPGA by Abbas Y.A., Jidin R., Jamil N., Z'aba M.R., Rusli M.E., Tariq B.

    Published 2023
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  7. 7
    Performance evaluation of real-time multiprocessor scheduling algorithms

    Performance evaluation of real-time multiprocessor scheduling algorithms by Alhussian, H., Zakaria, N., Abdulkadir, S.J., Fageeri, S.O.

    Published 2016
    “…We hyave used the CPU profiler of Oracle JavaTM VisualVM to monitor the execution of LRE-TL as well as USG algorithms. …”
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  8. 8
    Visdom: Smart guide robot for visually impaired people

    Visdom: Smart guide robot for visually impaired people by Lee, Zhen Ting

    Published 2025
    “…An Android mobile application, developed using Java and the java.net.Socket library, provides an intuitive and accessible user interface for seamless interaction with the robot. …”
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  9. 9
    Cryptographic protection of block-oriented storage devices using AES-XTS in FPGA

    Cryptographic protection of block-oriented storage devices using AES-XTS in FPGA by Ahmed, Shakil

    Published 2013
    “…Also the parallel AES-XTS encryption and decryption design were used to develop integrated chip of AES-XTS on FPGA. …”
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  10. 10
    Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture

    Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture by Chang, Boon Chiao

    Published 2018
    “…CPU implementations are becoming less efficient in handling the computation of crypto algorithms. Hence, other contemporary processor architectures such as GPU and FPGA have become popular alternative to speed up the computation in recent years.This dissertation first discusses several existing large integer multiplication algorithms and reviews different methods used to implement thediscussed algorithms done by other researchers in both Graphic Processing Unit (GPU) and Field Programmable Gate Array (FPGA).Compared to GPU, FPGA offered more low level design and development to the implementation. …”
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  11. 11
    Web-based RIG performance reporting system using interactive visualization techniques / Amir Hambaly Nasaruddin

    Web-based RIG performance reporting system using interactive visualization techniques / Amir Hambaly Nasaruddin by Nasaruddin, Amir Hambaly

    Published 2019
    “…D3.js is used as a technology to visualize the result in interactive form or dynamic visualization which is a JavaScript library and Python is a language to program the system. …”
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  12. 12
    Enhanced bibliographic data retrieval and visualization using query optimization and spectral centrality measure

    Enhanced bibliographic data retrieval and visualization using query optimization and spectral centrality measure by Ramasamy, Chitra, Zolkepli, Maslina

    Published 2019
    “…This study proposing an enhance bibliographic data retrieval and visualization using hybrid clustering method consists of K-harmonic mean (KHM) and Spectral Algorithm and eigenvector centrality measure. …”
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  13. 13
    Mathematical simulation for 3-dimensional temperature visualization on open source-based grid computing platform

    Mathematical simulation for 3-dimensional temperature visualization on open source-based grid computing platform by Alias, Norma, Satam, Noriza, Abd. Ghaffar, Zarith Safiza, Darwis, Roziha, Hamzah, Norhafiza, Islam, Md. Rajibul

    Published 2009
    “…The development of this architecture is based on several programming language as it involves algorithm implementation on C, parallelization using Parallel Virtual Machine (PVM) and Java for web services development. …”
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  14. 14
    Design Of Robot Motion Planning Algorithm For Wall Following Robot

    Design Of Robot Motion Planning Algorithm For Wall Following Robot by Ali Hassan, Muhamad Khairul

    Published 2006
    “…Algorithms are developed for a simulated mobile robot that uses an array of range finders for navigation. …”
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  15. 15
    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design

    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

    Published 2024
    “…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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  16. 16
    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design

    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

    Published 2024
    “…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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  17. 17
    Dynamic force-directed graph with weighted nodes for scholar network visualization

    Dynamic force-directed graph with weighted nodes for scholar network visualization by Mohd. Aris, Khalid Al-Walid, Ramasamy, Chitra, Mohd Aris, Teh Noranis, Zolkepli, Maslina

    Published 2022
    “…The approach is realized by creating a web-based interface using D3 JavaScript algorithm that allows the visualization to focus on how data are connected to each other more accurately than the conventional lines of data seen in traditional data representation. …”
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  18. 18
    Enhancing obfuscation technique for protecting source code against software reverse engineering

    Enhancing obfuscation technique for protecting source code against software reverse engineering by Mahfoudh, Asma

    Published 2019
    “…There is also a need to develop a tool that contains the three approaches where the developer can customize the protection of the source code.…”
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  19. 19
    Graphical user interface for bounded-addition fuzzy splicing systems and their variants / Mathuri Selvarajoo ... [et al.]

    Graphical user interface for bounded-addition fuzzy splicing systems and their variants / Mathuri Selvarajoo ... [et al.] by Selvarajoo, Mathuri, Santono, Mohd Pawiro, Fong, Wan Heng, Sarmin, Nor Haniza

    Published 2023
    “…In this research, a graphical user interface is developed to generate all the splicing languages generated by bounded-addition fuzzy splicing systems and their variants. An algorithm is developed using JAVA and Visual Studio Code software in order to replace the time-consuming manual computation of the languages generated by bounded-addition fuzzy DNA splicing systems and their variants.…”
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  20. 20
    Development Of Machine Learning User Interface For Pump Diagnostics

    Development Of Machine Learning User Interface For Pump Diagnostics by Lee, Zhao Yang

    Published 2022
    “…Build up a user interface by using Visual Studio Code (VSC) to run the coding of Cascading Style Sheet (CSS), Hyper Text Markup Language (HTML) and JavaScript (JS) as a webpage and connect to Azure Machine Learning Model and this will allow the user from using the model from a webpage when they have active internet with any devices.…”
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