Search Results - (( development programme detection algorithm ) OR ( java optimization path algorithm ))

Refine Results
  1. 1

    Embedded system for indoor guidance parking with Dijkstra’s algorithm and ant colony optimization by Mohammad Ata, Karimeh Ibrahim

    Published 2019
    “…BST inserts the nodes in the way that the Dijkstra’s can find the empty parking in fastest way. Dijkstra’s algorithm initials the paths to finding the shortest path while ACO optimizes the paths. …”
    Get full text
    Get full text
    Thesis
  2. 2

    SecPath: Energy efficient path reconstruction in wireless sensor network using iterative smoothing by Abd, Wamidh Jwdat

    Published 2019
    “…This work uses iterative smoothing algorithm to find an alternative path with less distance and energy consumption. …”
    Get full text
    Get full text
    Thesis
  3. 3

    Energy efficient path reconstruction in wireless sensor network using iPath by Hasan, Sazlinah, Abd, Wamidh Jwdat, Ariffin, Ahmad Alauddin

    Published 2019
    “…This work uses iterative boosting algorithm to find an alternative path with less distance and energy consumption. …”
    Get full text
    Get full text
    Get full text
    Article
  4. 4

    Visdom: Smart guide robot for visually impaired people by Lee, Zhen Ting

    Published 2025
    “…Core functionalities such as path planning, autonomous movement, voice feedback, and app-to-robot communication have been thoroughly tested and optimized. …”
    Get full text
    Get full text
    Final Year Project / Dissertation / Thesis
  5. 5

    Real time motorcycle image detections on field programmable gate array by Mat Nong, Mohd Ali, Osman, Rosiah, Md Yusof, Juraina, Mohd Sidek, Roslina

    Published 2015
    “…Development of real time motorcycle image detections on field programmable architecture is presented in this paper. …”
    Get full text
    Get full text
    Conference or Workshop Item
  6. 6

    Implementation of Real-time Simple Edge Detection on FPGA by Mohd Shukor, Mohd Nasir, Lo, H. H., Sebastian , Patrick

    Published 2005
    “…The chosen image processing algorithms implemented was edge detection. This work utilizes Altera DE2 development board powered by Cyclone II FGPA pair with 1.3 Mega pixel CMOS camera from Terasic Technologies. …”
    Get full text
    Get full text
    Conference or Workshop Item
  7. 7

    Implementation of real-time simple edge detection on FPGA by P., Sebastian, M.N.B.M., Shukor, H.H., Lo

    Published 2007
    “…The chosen image processing algorithms implemented was edge detection. This work utilizes Altera DE2 development board powered by Cyclone II FGPA pair with 1.3 Mega pixel CMOS camera from Terasic Technologies. …”
    Get full text
    Get full text
    Get full text
    Conference or Workshop Item
  8. 8

    IMAGE PROCESSING ALGORITHMS ON FPGA by MOHAMED SHUKOR, MOHAMED NASIR

    Published 2007
    “…The objective of this project is to construct a real time hardware image processing system which based on Field Programmable Gate Array (FPGA). The chosen image processing algorithms are implemented on two systems which are Color Filtering System and Edge Detection System. …”
    Get full text
    Get full text
    Final Year Project
  9. 9
  10. 10

    Design and implementation of multimedia digital matrix system by Chui, Yew Leong, Ramli, Abdul Rahman, Perumal, Thinagaran, Sulaiman, Mohd Yusof, Ali, Mohd Liakot

    Published 2005
    “…Due to the issues of signal integrity in high-speed digital design, a new adaptive channel synchronization algorithm has been developed. The algorithm, named as hybrid-reset algorithm utilizes the nature of asynchronous reset to compensate the drawback of synchronous counter for phase detection. …”
    Get full text
    Get full text
    Conference or Workshop Item
  11. 11
  12. 12

    Low area Programmable Memory Built-In Self-Test (PMBIST) for small embedded ram cores / Nur Qamarina Mohd Noor by Mohd Noor, Nur Qamarina

    Published 2013
    “…The memory BIST applies various test algorithms such as MARCH tests to detect various RAM faults. …”
    Get full text
    Get full text
    Thesis
  13. 13

    Development of a steady state visual evoked potential (SSVEP)-based brain computer interface (BCI) system by Leow, R.S., Ibrahim, F., Moghavvemi, M.

    Published 2007
    “…This paper describes the development of a synchronous, online brain computer interface (BCI) system based on detecting the steady-state visual evoked potential (SSVEP). …”
    Get full text
    Get full text
    Get full text
    Conference or Workshop Item
  14. 14

    Design and analysis of high performance matrix filling for DNA sequence alignment accelerator using asic design flow: article / Nurzaima Mahmod by Mahmod, Nurzaima

    “…To optimize the performance of the algorithm by exploiting parallelism in the design several techniques have been developed. …”
    Get full text
    Get full text
    Article
  15. 15

    SIMULATION AND ANALYSIS OF HARMONIC DETECTION AND MITIGATION SYSTEM USING ACTIVE FILTER by MIZA, BELIA

    Published 2019
    “…The main objective for this study is to analyse the harmonics components in AC power system using Fast Fourier Transforms (FFT) algorithm. Other than that, the objective is also to design and develop the harmonic detection system for power quality of AC power system. …”
    Get full text
    Get full text
    Get full text
    Final Year Project Report / IMRAD
  16. 16

    MBIST implementation and evaluation in FPGA based on low-complexity March algorithms by Jidin, Aiman Zakwan, Mispan, Mohd Syafiq, Hussin, Razaidi, Weng, Fook Lee

    Published 2024
    “…This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. …”
    Get full text
    Get full text
    Get full text
    Article
  17. 17

    A step towards the development of VHDL model for ANN based EMG signal classifier by Ahsan, Md. Rezwanul, Ibrahimy, Muhammad Ibn, Khalifa, Othman Omran

    Published 2012
    “…VHDL (Very High Speed Integrated Circuit Hardware Description Language) has been used to model the algorithm and which can be implemented into the target device FPGA (Field Programmable Gate Array). …”
    Get full text
    Get full text
    Get full text
    Proceeding Paper
  18. 18

    Preliminary study on fault detection using artificial neural network for water-cooled reactors by Abdul Karim, Julia, Lanyau, Tony, Maskin, Masleha, Anuar, M. A. S., Che Soh, Azura, Abdul Rahman, Ribhan Zafira

    Published 2020
    “…This work was carried out to discover the use of an artificial neural network (ANN) to model and develop a fault detection programme in the RTP cooling system. …”
    Get full text
    Get full text
    Get full text
    Article
  19. 19

    Design and analysis of high performance matrix filling for DNA sequence alignment accelerator using ASIC design flow / Nurzaima Mahmod by Mahmod, Nurzaima

    Published 2010
    “…To optimize the performance of the algorithm by exploiting parallelism in the design several techniques have been developed. …”
    Get full text
    Get full text
    Thesis
  20. 20

    Evolutionary cost-cognizant regression test case prioritization for object-oriented programs by Bello, AbdulKarim

    Published 2019
    “…Therefore, this study proposed a cost-cognizant TCP approach for object-oriented software that uses path-based integration testing to identify the possible execution path extracted from the Java System Dependence Graph (JSDG) model of the source code using forward slicing technique. …”
    Get full text
    Get full text
    Thesis