Search Results - (( development programme boost algorithm ) OR ( java optimization sensor algorithm ))

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  1. 1

    SecPath: Energy efficient path reconstruction in wireless sensor network using iterative smoothing by Abd, Wamidh Jwdat

    Published 2019
    “…Wireless sensor networks operate through commonly self-organized sensor nodes to transfer data in a multi-hop approach to a central sink. …”
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  2. 2

    Energy efficient path reconstruction in wireless sensor network using iPath by Hasan, Sazlinah, Abd, Wamidh Jwdat, Ariffin, Ahmad Alauddin

    Published 2019
    “…Wireless sensor networks operate through commonly self-organized sensor nodes to transfer data in a multi-hop approach to a central sink. …”
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  3. 3
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    Collaborative-based web recommender system for community-driven homestay programmes by Miraz, Mahadi Hasan

    Published 2017
    “…All these operations are carried out simultaneously to boost the functions of the CBWR system. Hence, this research contributes to the development of a specific unique web database and a CBWR system, which is adopted from collaborative algorithm. …”
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  5. 5

    Anfis Modelling On Diabetic Ketoacidosis For Unrestricted Food Intake Conditions by Saraswati, Galuh Wilujeng

    Published 2017
    “…The project has also implemented the optimization process onto the proposed ANFIS model through the hybrid of Genetic Algorithm on the fuzzy membership function of the ANFIS model. …”
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  6. 6

    Instruction Set Extension Of A Low-End Reconfigurable Microcontroller In Bit-Sorting Implementation by Salim, Sani Irwan, Soo, Yew Guan, Samsudin, Sharatul Izah

    Published 2018
    “…The modules’ integration is implemented using instruction set architecture (ISA) extension technique and is developed on the Field Programmable Gate Array (FPGA). …”
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  7. 7

    Application Specific Instruction Set Processor (ASIP) Design In An 8-Bit Softcore Microcontroller by Salim, Sani Irwan, Soo, Yew Guan, Samsudin, Sharatul Izah

    Published 2018
    “…The modules’ integration is implemented using ASIP design without occurring extra board space and is developed using the Field Programmable Gate Array (FPGA) as the single chip solutions. …”
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