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  1. 1

    Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation by Ismail, Mohd. Izuan

    Published 2006
    “…The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). …”
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    Thesis
  2. 2

    Enhancing performance of XTS cryptography mode of operation using parallel design by Ahmed Alomari, Mohammad

    Published 2009
    “…Performance evaluation shows that XTS exhibits faster speed when an RC6 encryption algorithm is used, compared to other encryption algorithms such as AES and Twofish. …”
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    Thesis
  3. 3

    Design and Implementation of Advanced Encryption Standard Using Verilog HDL by Shamsiah, Suhaili, Rene Brooke, Fredrick, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2020
    “…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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    Article
  4. 4

    Campus safe: Safeguarding GPS-based Physical Identity and Access Management (PIAM) system with a lightweight Geo-Encryption by Yeo Zi Zian

    Published 2022
    “…The selected lightweight geo-encryption algorithm will be implemented in the proposed system, vi which develops by using Java language. …”
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    Academic Exercise
  5. 5

    Design and implementation of advanced encryption standard using verilog HDL by Shamsiah, Suhaili, Fredrick, Rene Brooke, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2022
    “…The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. …”
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    Conference or Workshop Item
  6. 6

    A hardware implementation of Rivest-Shamir-Adleman co-processor for resource constrained embedded systems by Paniandi, Arul

    Published 2006
    “…Upon verification, a demonstration application prototype that performs RSA encryption and decryption is developed using Visual Basic 6.0. …”
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    Thesis
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    Performance evaluation of real-time multiprocessor scheduling algorithms by Alhussian, H., Zakaria, N., Abdulkadir, S.J., Fageeri, S.O.

    Published 2016
    “…These results suggests that optimal algorithms may turn to be non-optimal when practically implemented, unlike USG which reveals far less scheduling overhead and hence could be practically implemented in real-world applications. …”
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    Conference or Workshop Item
  10. 10

    Route Optimization System by Zulkifli, Abdul Hayy

    Published 2005
    “…After much research into the many algorithms available, and considering some, including Genetic Algorithm (GA), the author selected Dijkstra's Algorithm (DA). …”
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    Final Year Project
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    Cryptographic protection of block-oriented storage devices using AES-XTS in FPGA by Ahmed, Shakil

    Published 2013
    “…Also the parallel AES-XTS encryption and decryption design were used to develop integrated chip of AES-XTS on FPGA. …”
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    Thesis
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    Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture by Chang, Boon Chiao

    Published 2018
    “…CPU implementations are becoming less efficient in handling the computation of crypto algorithms. Hence, other contemporary processor architectures such as GPU and FPGA have become popular alternative to speed up the computation in recent years.This dissertation first discusses several existing large integer multiplication algorithms and reviews different methods used to implement thediscussed algorithms done by other researchers in both Graphic Processing Unit (GPU) and Field Programmable Gate Array (FPGA).Compared to GPU, FPGA offered more low level design and development to the implementation. …”
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    Final Year Project / Dissertation / Thesis
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    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

    Published 2024
    “…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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    Article
  18. 18

    Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

    Published 2024
    “…It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. …”
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    Article
  19. 19

    Computer Lab Timetabling Using Genetic Algorithm Case Study - Unit ICT by Abdullah, Amran

    Published 2006
    “…Genetic Algorithm is one of the most popular optimization solutions used in various applications such as scheduling. …”
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    Thesis
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