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Development of low power viterbi decoder on complex programmable logic device platform by Abu, Mohd Azlan

“…Consequently, the number of logic gates and the total power consumption of the STTC Viterbi decoder can be reduced by using the new algorithms. The proposed algorithms have been designed and implemented by using MATLAB, Altera Quartus 2 and Altera MAX V CPLD board. …”
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Effective downlink resource management for wimax networks by Shareef, Zayd Ashraf Najeeb

“…Our EDRM framework involves three functions: Class-Based Scheduling (CBS) algorithm, Dynamic Bandwidth Allocation (DBA) scheme and Link Session Management (LSM) policy. …”
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Automatic marking system for programming subject by Chan, Jin Yee

“…This project is a web application designed for lecturer that teaching programming subject to automatically mark programming algorithm exercise. …”
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Designing and Developing an Intelligent Congkak by Muhammad Safwan, Mohd Shahidan

“…and “Can Min-Max algorithm (MM) be speeded up by using NN as a forward-pruning method?”. …”
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Development of computer aided three-dimensional geometric modeler based on designer's idea in twodimensional by Haron, Habibollah

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Adaptive resource allocation algorithms with QoS support in OFDMA-based WiMAX networks by Alsahag, Ali Mohamemed Mansor

“…The aim of this thesis is to develop a fair and effi- cient packet scheduling and adaptive multiuser frequency-time domain resources allocation algorithms to support QoS for a diverse service class in OFDMA based IEEE 802.16 network. …”
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Development of a hybrid dynamic fuzzy encoder and decoder model for colour QR code by Badawi, Bakri

“…A new colour QR code algorithm known as a Fuzzy QR code (FQR code) was proposed to solve the problems faced by current colour QR codes. …”
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Design And Implementation Of Low Passband Ripple Digital Down Converter Filter For Software Defined Radio Transceiver by Naghmash, Majid Salal

“…The proposed DDC filters incorporate of Remez algorithm and Mini-max algorithm to reduce the error rate in the filter response. …”
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Wavelet coding design for image data compression by Khalifa, Othman Omran

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Design Of FPGA-Based Encryption Chipusing Blowfish Algorithm by Khor, Lay Hoong

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Multilayers fast mode decision algorithm for scalable video coding: design, implementation, and streaming evaluation on IEEE 802.11g wireless LAN by Maarif, Haris Al Qodri, Gunawan, Teddy Surya

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A study on channel coding for 5G / Xu Wei by Xu , Wei

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Enhanced algorithms for three-dimensional object interpreter by Haron, Habibollah

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Development of generic algorithm in wheel-typed hybrid rocket grain design for performance estimation by Kafafy, Raed, Azami, Muhammad Hanafi, Idres, Moumen, Zaharim, Azami, Sopian, Kamaruzaman

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New Fast Block Matching Algorithm Using New Hybrid Search Pattern And Strategy To Improve Motion Estimation Process In Video Coding Technique by Hamid, Nurul 'Atiqah

“…Up until today, video compression algorithm has been applied in various video applications ranging from video conferencing to video telephony. …”
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Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

“…This article analyses a fast implementation of the Hash-based Message Authentication Code (HMAC), which uses its algorithm to ensure the validity and integrity of data to optimise hardware efficiency and design efficacy using the SHA-256 algorithm. …”
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Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design by Shamsiah, Suhaili, Norhuzaimin, Julai, Rohana, Sapawi, Nordiana, Rajaee

“…This article analyses a fast implementation of the Hash-based Message Authentication Code (HMAC), which uses its algorithm to ensure the validity and integrity of data to optimise hardware efficiency and design efficacy using the SHA-256 algorithm. …”
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MBIST implementation and evaluation in FPGA based on low-complexity March algorithms by Jidin, Aiman Zakwan, Mispan, Mohd Syafiq, Hussin, Razaidi, Weng, Fook Lee

“…They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. …”
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Another perspective in generating and using gray code word by Ahmad, Anita

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Object-Oriented Programming semantics representation utilizing agents by Mohd Aris, Teh Noranis

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