Search Results - (( developing cell sizing algorithm ) OR ( java implementation modified algorithm ))
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Direct approach for mining association rules from structured XML data
Published 2012“…The thesis also provides a two different implementation of the modified FLEX algorithm using a java based parsers and XQuery implementation. …”
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OPTIMIZED MIN-MIN TASK SCHEDULING ALGORITHM FOR SCIENTIFIC WORKFLOWS IN A CLOUD ENVIRONMENT
Published 2023“…To achieve this, we propose a new noble mechanism called Optimized Min-Min (OMin-Min) algorithm, inspired by the Min-Min algorithm. The objectives of this work are: i) to provide a comprehensive review of the cloud and scheduling process; ii) to classify the scheduling strategies and scientific workflows; iii) to implement our proposed algorithm with various scheduling algorithms (i.e., Min-Min, Round-Robin, Max-Min, and Modified Max-Min) for performance comparison, within different cloudlet sizes (i.e., small, medium, large, and heavy) in three scientific workflows (i.e., Montage, Epigenomics, and SIPHT); and iv) to investigate the performance of the implemented algorithms by using CloudSim. …”
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A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
Published 1997“…To deal with cells of various size , the algorithm progresses by moving one cell at a time between the blocks of the partition while maintaining a desired based on the size of the blocks rather than the number of cells per block. …”
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Prevention And Detection Mechanism For Security In Passive Rfid System
Published 2013“…The proposed protocol is designed with lightweight cryptographic algorithm, including XOR, Hamming distance, rotation and a modified linear congruential generator (MLCG). …”
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Automatic generation of content security policy to mitigate cross site scripting
Published 2016“…It can be extended to support generating CSP for contents that are modified by JavaScript after loading. Current approach inspects the static contents of URLs.…”
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A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
Published 2008“…This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. …”
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A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
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Genetic algorithms for VLSI micro-Cell layout area optimization based on binary tree
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An image segmentation algorithm for measurement of flotation froth bubble size distributions
Published 2017“…The bubble size distribution at the froth surface of a flotation cell is closely related to the process condition and performance. …”
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A Comparative Study of Some Cellular Manufacturing Techniques
Published 2000“…The techniques were used to develop cells for matrices from various sizes of parts and machines. …”
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Design of power device sizing and integration for solar-powered aircraft application
Published 2021“…The power device was developed with the PV cell Maxeon Gen III for high efficiency, the rechargeable battery sulfur-lithium battery for high energy density, and the Maximum power point tracker neural network algorithm for smart and efficient response. …”
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Design of power device sizing and integration for solar-powered aircraft application / Safyanu Bashir Danjuma, Zamri Omar and Mohd Noor Abdullah
Published 2021“…The power device was developed with the PV cell Maxeon Gen III for high efficiency, the rechargeable battery sulfur-lithium battery for high energy density, and the Maximum power point tracker neural network algorithm for smart and efficient response. …”
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Application Of Neural Network In Malaria Parasites Classification
Published 2006“…Hybrid Multilayer Perceptron (HMLP) network with modified recursive prediction error algorithm will be developed using Borland C++ Builder. …”
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Monograph -
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Adaptive persistence layer for synchronous replication (PLSR) in heterogeneous system
Published 2011“…The PLSR architecture model, workflow and algorithms are described. The PLSR has been developed using Java Programming language. …”
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Low Power Standard Cell Library Design For Application Specific Integrated Circuit
Published 2002“…This requires chip designers to minimize power consumption at all design level such as system, algorithm, architecture, circuit and technology. The objective of this work is to develop low power CMOS standard cell library to be used in application specific integrated circuit (ASIC) design flow. …”
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