Search Results - (( developing cell sizing algorithm ) OR ( java application customization algorithm ))
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A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
Published 1997“…To deal with cells of various size , the algorithm progresses by moving one cell at a time between the blocks of the partition while maintaining a desired based on the size of the blocks rather than the number of cells per block. …”
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A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
Published 2008“…This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. …”
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A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
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Genetic algorithms for VLSI micro-Cell layout area optimization based on binary tree
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An image segmentation algorithm for measurement of flotation froth bubble size distributions
Published 2017“…The bubble size distribution at the froth surface of a flotation cell is closely related to the process condition and performance. …”
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A Comparative Study of Some Cellular Manufacturing Techniques
Published 2000“…The techniques were used to develop cells for matrices from various sizes of parts and machines. …”
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Design of power device sizing and integration for solar-powered aircraft application
Published 2021“…The power device was developed with the PV cell Maxeon Gen III for high efficiency, the rechargeable battery sulfur-lithium battery for high energy density, and the Maximum power point tracker neural network algorithm for smart and efficient response. …”
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Design of power device sizing and integration for solar-powered aircraft application / Safyanu Bashir Danjuma, Zamri Omar and Mohd Noor Abdullah
Published 2021“…The power device was developed with the PV cell Maxeon Gen III for high efficiency, the rechargeable battery sulfur-lithium battery for high energy density, and the Maximum power point tracker neural network algorithm for smart and efficient response. …”
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Application Of Neural Network In Malaria Parasites Classification
Published 2006“…Hybrid Multilayer Perceptron (HMLP) network with modified recursive prediction error algorithm will be developed using Borland C++ Builder. …”
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Low Power Standard Cell Library Design For Application Specific Integrated Circuit
Published 2002“…This requires chip designers to minimize power consumption at all design level such as system, algorithm, architecture, circuit and technology. The objective of this work is to develop low power CMOS standard cell library to be used in application specific integrated circuit (ASIC) design flow. …”
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Development of automated neighborhood pattern sensitive faults syndrome generator for static random access memory
Published 2011“…This tool can be used to ease the process of developing a new March test algorithm for NPSF.…”
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Design and development of high performance swa cell design for local DNA sequence alignment
Published 2017“…Moreover, the minimal size of the two bit data representation characters format used in the design has resulted in minimizing the temporary memory requirement in the cell design up to 75%. …”
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Review on the Recent Developments of Photovoltaic Thermal (PV/T) and Proton Exchange Membrane Fuel Cell (PEMFC) Based Hybrid System
Published 2016“…There are less study on the both power and heat utilization which is indeed necessary in future development in term of operation strategy, optimization of size, and operation algorithm…”
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Enhancing obfuscation technique for protecting source code against software reverse engineering
Published 2019“…The proposed technique can be enhanced in the future to protect games applications and mobile applications that are developed by java; it can improve the software development industry. …”
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