Search Results - (( developing a bit algorithm ) OR ( java simulation optimization algorithm ))
Search alternatives:
-
1
Attribute reduction based scheduling algorithm with enhanced hybrid genetic algorithm and particle swarm optimization for optimal device selection
Published 2022“…The simulation is implemented with iFogSim and java programming language. …”
Get full text
Get full text
Article -
2
Enhancement of Ant Colony Optimization for Grid Job Scheduling and Load Balancing
Published 2011“…Global pheromone update is performed after the completion of processing the jobs in order to reduce the pheromone value of resources. A simulation environment was developed using Java programming to test the performance of the proposed EACO algorithm against existing grid resource management algorithms such as Antz algorithm, Particle Swarm Optimization algorithm, Space Shared algorithm and Time Shared algorithm, in terms of processing time and resource utilization. …”
Get full text
Get full text
Get full text
Thesis -
3
Ant colony optimization algorithm for load balancing in grid computing
Published 2012“…The proposed algorithm is known as the enhance ant colony optimization (EACO). …”
Get full text
Get full text
Get full text
Monograph -
4
OPTIMIZED MIN-MIN TASK SCHEDULING ALGORITHM FOR SCIENTIFIC WORKFLOWS IN A CLOUD ENVIRONMENT
Published 2023“…To achieve this, we propose a new noble mechanism called Optimized Min-Min (OMin-Min) algorithm, inspired by the Min-Min algorithm. …”
Review -
5
VHDL implementation of DES algorithm / Emmanvel Kajan Mering
Published 2004Get full text
Get full text
Thesis -
6
Embedded system for indoor guidance parking with Dijkstra’s algorithm and ant colony optimization
Published 2019“…This study proposes a car parking management system which applies Dijkstra’s algorithm, Ant Colony Optimization (ACO) and Binary Search Tree (BST) in structuring a guidance system for indoor parking. …”
Get full text
Get full text
Thesis -
7
Dynamic Feedback Flow Control Algorithms for Unicast and Multicast Available Bit Rate Service in Asynchronous Transfer Mode Networks
Published 2000“…Thirdly, the design and implementation issues have been addressed together with the major drawbacks of the previous schemes and hence two algorithms have been proposed. A dynamic rate-based flow control (DRFC) scheme has been developed to support ABR service in unicast environment, while an adaptive feedback consolidation (AFC) algorithm has been designed for ABR multicasting. …”
Get full text
Get full text
Thesis -
8
Features selection for intrusion detection system using hybridize PSO-SVM
Published 2016“…Hybridize Particle Swarm Optimization (PSO) as a searching algorithm and support vector machine (SVM) as a classifier had been implemented to cope with this problem. …”
Get full text
Get full text
Thesis -
9
Optimization of Digital Electronic Circuit Structure Design Using Genetic Algorithm
Published 2008“…A number of experiments are implemented to design 3-bit, 4-bit, 5-bit and 6-bit circuits. …”
Get full text
Get full text
Thesis -
10
A new 128-bit block cipher
Published 2009“…Towards that and after reviewing related research, in this research we propose to come up with a new 128-bit block cipher cryptographic algorithm which shall meet the security requirements. …”
Get full text
Get full text
Thesis -
11
Resource management in grid computing using ant colony optimization
Published 2011“…Resources with high pheromone value are selected to process the submitted jobs.Global pheromone update is performed after completion processing the jobs in order to reduce the pheromone value of resources.A simulation environment was developed using Java programming to test the performance of the proposed EACO algorithm against other ant based algorithm, in terms of resource utilization.Experimental results show that EACO produced better grid resource management solution.…”
Get full text
Get full text
Get full text
Get full text
Monograph -
12
16 bits x 16 bits booth multiplier using VHDL
Published 2008“…The designed digital system will receive two 16 bits input and processes it to create a 32 bits output with the value of the multiplied inputs data value. …”
Get full text
Get full text
Undergraduates Project Papers -
13
Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture
Published 2018“…To achieve certain level of security, Public Key Cryptography algorithm is performed on large integer that is more than 64-bit, typical bit size supported by conventional Central Processing Unit (CPU) (e.g. 512-bit for Elliptic Curve Cryptography (ECC), 2048-bit for Rivest-Shamir-Adleman (RSA) and million bits for Fully Homomorphic Encryption (FHE)). …”
Get full text
Get full text
Final Year Project / Dissertation / Thesis -
14
A Study And Development Of Digital Control Technique For Power Factor Correction Using Pre-Calculated Algorithm With A Low Cost 8-Bit Microcontroller
Published 2013“…The mature manufacturing technologies in digital devices has led to the proliferation of powerful yet low cost digital controllers and enable the possibility of digital power factor correction implementation in a more competitive way. A digital control technique for power factor correction using pre-calculated algorithm with a low cost 8-bit microcontroller is studied and presented in this paper. …”
Get full text
Get full text
Thesis -
15
Implementation of locust inspired scheduling algorithm with huge number of servers for energy efficiency in a cloud datacenter
Published 2019“…Cloudsim is used as Discrete Event Simulation tool and Java as coding language to evaluate LACE algorithm. …”
Get full text
Get full text
Thesis -
16
Instruction Set Extension Of A Low-End Reconfigurable Microcontroller In Bit-Sorting Implementation
Published 2018“…Extensive simulations were performed with the and a comprehensive methodology is proposed. It was found that the ISA extension from 12-bit to 16-bit has produced a faster execution time with fewer resource utilization when implementing the bit-sorting algorithm. …”
Get full text
Get full text
Get full text
Article -
17
Design of a floating point unit for 32-bit 5 stage pipeline processor
Published 2020“…Also, a dedicated register file is developed for FPU to store 32-bits or 64- bits of data. …”
Get full text
Get full text
Final Year Project / Dissertation / Thesis -
18
A novel embedding method to increase capacity and robustness of low-bit encoding audio steganography technique using noise gate software logic algorithm
Published 2010“…In this study, we developed a novel method that is able to shift the limit for transparent data hiding in audio from the fourth LSB layer to the eighth LSB layer, thus the method has improved the capacity and robustness of data hiding in the audio file using a two steps approach. …”
Get full text
Get full text
Get full text
Article -
19
Steganography based on utilizing more surrounding pixels
Published 2010“…The purpose of this study is to investigate the application of least significant bit insertion method (LSB) in concealing a definite amount of message bits inside a typical media such as an 8-bit gray-scale image and develop an alternative model structure selection algorithm based on considering more surrounding pixels in order to compute the best capacity value for each target pixel. …”
Get full text
Get full text
Thesis -
20
Analysis of parabolic antennas for radio telescopes and the development of encryption methods for radio astronomical images
Published 2022“…The results showed that this algorithm has better performance compared to other recently developed algorithms. …”
Get full text
Get full text
Final Year Project / Dissertation / Thesis
