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Implementation of High Speed Large Integer Multiplication Algorithm on Contemporary Architecture
Published 2018“…To achieve certain level of security, Public Key Cryptography algorithm is performed on large integer that is more than 64-bit, typical bit size supported by conventional Central Processing Unit (CPU) (e.g. 512-bit for Elliptic Curve Cryptography (ECC), 2048-bit for Rivest-Shamir-Adleman (RSA) and million bits for Fully Homomorphic Encryption (FHE)). …”
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Final Year Project / Dissertation / Thesis -
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Dynamic Feedback Flow Control Algorithms for Unicast and Multicast Available Bit Rate Service in Asynchronous Transfer Mode Networks
Published 2000“…Thirdly, the design and implementation issues have been addressed together with the major drawbacks of the previous schemes and hence two algorithms have been proposed. A dynamic rate-based flow control (DRFC) scheme has been developed to support ABR service in unicast environment, while an adaptive feedback consolidation (AFC) algorithm has been designed for ABR multicasting. …”
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Thesis -
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16 bits x 16 bits booth multiplier using VHDL
Published 2008“…The designed digital system will receive two 16 bits input and processes it to create a 32 bits output with the value of the multiplied inputs data value. …”
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Undergraduates Project Papers -
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A new 128-bit block cipher
Published 2009“…The existence of this new 128-bit block cipher algorithm will increase the protection of the national information infrastructure and also will contribute as an alternative to other cryptographic algorithms in security in the computing industry.…”
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Thesis -
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A novel embedding method to increase capacity and robustness of low-bit encoding audio steganography technique using noise gate software logic algorithm
Published 2010“…Audio quality evaluation has used to evaluate our purposed method in two ways. First, objective test showed the algorithm succeeds in this task, while increasing SNR values of our algorithm comparing to SNR values obtained by standard LSB embedding in the 8th bits LSB layer and the comparison of the histogram audio excerpts has proved this also. …”
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Article -
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Enhanced scalar multiplication algorithm over prime field using elliptic net
Published 2024“…On 512 bits with similar comparison, the designed algorithm exhibited better performance by averages 59.2%, 31.0% and 13.2%. …”
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Improved algorithms of elliptic curve point multiplication over binary and prime fields using elliptic net
Published 2022“…For safe curves of 384 and 512 bits, the developed ENPM algorithm over prime field outperformed the BM algorithm in terms of overall multiplications with 57.60% and 59.16% average running time. …”
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Thesis -
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Performance Analysis Of Different Hash Functions Using Bloom Filter For Network Intrusion Detection Systems In 32-Bit And 64-Bit Computer Operation Mode.
Published 2016“…A Bloom Filter pattern matching algorithm with fast hashing functions is developed for 32-bit and 64-bit computer system. …”
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Thesis -
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Hardware Implementation Of Rc4a Stream Cipher Algorithm
Published 2007“…The implementation is able to support variable key lengths from 8 bits up to 512 bits. Unlike other stream ciphers, the proposed implementation generates two output streams at a time, whereas others generate only one output stream. …”
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Thesis -
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Optimization of Motion Compensated Block-Based DCT Video Compression for Software Implementation
Published 2000“…Then, various optimized algorithms for the two core processes in the compression, DCT and motion estimation, were reviewed and analyzed. …”
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Thesis -
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Comparative analysis of Selective Clonal Mutation with conventional GA operators in solar tracking environment
Published 2023Conference Paper -
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Proposed method for enhancing quantum bit error rate using quantum key distribution technique
Published 2014“…This paper is proposed to provide a way for solving the key transmission issues using qkd, as a new method, by providing two quantum channels to improve qber. In addition also to develop an algorithm for integrating pki and qkd in solving the secrete key sharing issues in grid environment. …”
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Conference or Workshop Item -
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Booth’s Algorithm Design Using Field Programmable Gate Array
Published 2014“…The high speed operation and less space and energy required had made the digital devices more preferred.This project is to design digital system which performed fixed point Booth Multiplier Algorithm where the design system would be developed using hardware description language (HDL),in this case,VHDL (VHSIC Hardware Description Language),VHSIC stands for Very High Speed Integrated Circuit.In this project would be used Xilinx ISE 10.1which is the software used to designed digital system for Xilinx manufactured FPGA board.In Xilinx have two main languages which are VHDL and Verilog.For design Booth’s Multiplier Algorithm we used Verilog code which is has to create the program module and test bench.In that case,to design digital system will have input and output which is input is 8 bits and output is 16 bits.Finally, it is proven that the system created can calculate and yield a fixed point multiplied output of the input value. …”
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Article -
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