Search Results - (( code classification modified algorithm ) OR ( parallel optimization max algorithm ))

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  1. 1
    Parallel implementation of genomic sequences classification using modified gabor wavelet transform on multicore systems

    Parallel implementation of genomic sequences classification using modified gabor wavelet transform on multicore systems by Gunawan, Teddy Surya, Ambikairajah, Eliathamby

    Published 2012
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  2. 2
    A Modified Hopfield Neural Network Algorithm (MHNNA) Using ALOS Image for Water Quality Mapping

    A Modified Hopfield Neural Network Algorithm (MHNNA) Using ALOS Image for Water Quality Mapping by Ahmed Asal Kzar, Ahmed Asal Kzar, M Jafri, Mohd Zubir, Mutter, Kussay N., Anwar, Saumi Syahreza

    Published 2016
    “…The TSS map was color-coded for visual interpretation. The efficiency of the proposed algorithm was investigated by dividing the validation data into two groups. …”
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  3. 3
    Parallel implementation of genomic sequences classification using modified Gabor wavelet transform on multicore systems

    Parallel implementation of genomic sequences classification using modified Gabor wavelet transform on multicore systems by Gunawan, Teddy Surya, Ambikairajah, Eliathamby

    Published 2012
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    Working Paper
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  4. 4
    Pemetaan Pm10 Dan Aot Menggunakan Teknik Penderiaan Jauh Di Semenanjung Malaysia

    Pemetaan Pm10 Dan Aot Menggunakan Teknik Penderiaan Jauh Di Semenanjung Malaysia by San, Limhwee

    Published 2006
    “…The developed algorithms are two-band algorithm, terma linear and modified algorithm from the combination of the visible and infrared thermal bands. …”
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    Thesis
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  5. 5
    Development of a modified adaptive protection scheme using machine learning technique for fault classification in renewable energy penetrated transmission line

    Development of a modified adaptive protection scheme using machine learning technique for fault classification in renewable energy penetrated transmission line by Olufemi, Osaji Emmanuel

    Published 2020
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  6. 6
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). …”
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