Search Results - (( _ constructing parallel algorithm ) OR ( program implementation using algorithm ))

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  1. 1

    A parallel version of a binary method and vector addition chains precomputation for exponentiation in RSA / Siti Khatijah Nor Abdul Rahim and Siti Rozanae Ismail by Abdul Rahim, Siti Khatijah Nor, Ismail, Siti Rozanae

    Published 2006
    “…Precomputing some of the powers is an option to speed up exponentiation which can save time too. However, we also constructed an algorithm for a parallel version of Vector Addition Chains to enhance the performance. …”
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    Research Reports
  2. 2

    Parallel Implementation of Two Level Barotropic Models Applied to the Weather Prediction Problem by Bahri, Susila

    Published 2004
    “…Then the parallel algorithms are constructed and run using the Beowulf Cluster machine. …”
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    Thesis
  3. 3

    Parallel Block Methods for Solving Ordinary Differential Equations by Abdul Majid, Zanariah

    Published 2004
    “…The new codes were then used for the parallel implementation in solving large systems of first and higher order ODEs. …”
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    Thesis
  4. 4

    Image based autonomous indoor parallel parking assist on omni-directional vehicle (ODV) by Edwind, Liaw Yee Kang

    Published 2016
    “…The image processing algorithm is first developed using Visual Studio C++ and OpenCV. …”
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    Undergraduates Project Papers
  5. 5

    OPTIMIZATION OF TWO FISH ENCRYPTION ALGORITHM ON FPGA by DORE RAJA, ANAND A RAJA

    Published 2004
    “…Both Design I and Design 2 were written using VHDL, simulated using ALDEC, synthesized using XILINX Synthesizing Tools, implemented using XILINX ISE6.2i implementation tools and download onto the Spartan 2 FPGA board using BEDLOAD utility program. …”
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    Final Year Project
  6. 6

    A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors by Lee, Weng Fook

    Published 2008
    “…An adder algorithm using repetitive constructs in a parallel algorithm that allows for efficient and optimal synthesis for large data bus size is proposed as a suitable implementation for the adder within the ALU. …”
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    Thesis
  7. 7

    Optimization Of Twofish Encryption Algorithm On FPGA by Raja, Ananda Raja Dore, Zain Ali, Noohul Basheer, Hussin, Fawnizu Azmadi

    Published 2005
    “…Both Design I and Design 2 were written using VHDL, simulated using ALDEC, synthesized using XILINX Synthesizing Tools, implemented using XILINX ISE6.2i implementation tools and download onto the Spartan 2 FPGA board using BEDLOAD utility program. …”
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    Conference or Workshop Item
  8. 8

    Energy-aware task scheduling for streaming applications on NoC-based MPSoCs by Abd Ishak, Suhaimi Abd Ishak, Wu, Hui, Tariq, Umair Ullah

    Published 2024
    “…Our approach is supported by a set of novel techniques, which include constructing an initial schedule based on a list scheduling where the priority of each task is its approximate successor-tree-consistent deadline such that the workload across all the processors is balanced, a retiming heuristic to transform intraperiod dependencies into inter-period dependencies for enhancing parallelism, assigning an optimal discrete frequency for each task and each message using a Non-Linear Programming (NLP)-based algorithm and an Integer-Linear Programming (ILP)-based algorithm, and an incremental approach to reduce the memory usage of the retimed schedule in case of memory size violations. …”
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    Article
  9. 9

    CSC773 - Parallel Computing / College of Computing, Informatics And Media by UiTM, College of Computing, Informatics And Media

    Published 2023
    “…It emphasizes the decomposition and mapping techniques in constructing parallel algorithms. The parallel programming paradigms, namely, the shared address space and message passing are applied to implement parallel programs. …”
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    Teaching Resource
  10. 10

    Speeding up index construction with GPU for DNA data sequences by Rahmaddiansyah, , Abdul Rashid, Nur’aini

    Published 2011
    “…Graphic processor unit (GPU) is used to parallelize a segment of an indexing algorithm. In this research, we used a GPU to parallelize the sorting part of suffix array construction algorithm.Our results show that the GPU is able to accelerate the process of building the index of the suffix array by 1.68 times faster than without GPU.…”
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    Conference or Workshop Item
  11. 11

    On An Improved Parallel Construction Of Suffix Arrays For Low Bandwidth Pc-Cluster. by Kok, Jun Lee, Abdul Rashid, Nur'Aini, Abdullah, Rosni, Md. Ali, Norhashidah

    Published 2003
    “…An algorithm for the parallel construction of suffix arrays generation for any texts with larger alphabet size on distributed memory architecture is presented…”
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    Conference or Workshop Item
  12. 12

    Fast Finite Difference Time Domain Algorithms for Solving Antenna Application Problem by Hasan, Mohammad Khatim

    Published 2008
    “…Results show that these new sequential and parallel algorithms run faster than the standard sequential and parallel FDTD algorithms. …”
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    Thesis
  13. 13
  14. 14

    Implementation of Autonomous Vehicle Navigation Algorithms Using Event-Driven Programming by Saman, Abu Bakar Sayuti, Sebastian , Patrick, Malek, Nadhira, Hasidin, Nurul Zahidah

    Published 2012
    “…The algorithm can be relatively easy translated to a suitable program with event-driven programming technique. …”
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    Conference or Workshop Item
  15. 15

    Implementation of autonomous vehicle navigation algorithms using event-driven programming by Saman, Abu Bakar Sayuti, Sebastian , Patrick, Malek, Nadhira, Hasidin, Nurul Zahidah

    Published 2012
    “…The algorithm can be relatively easy translated to a suitable program with event-driven programming technique. …”
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    Conference or Workshop Item
  16. 16

    Evaluation of the effectiveness and efficiency of Wagner and Fischer algorithm in retrieving Hadith translated documents / Kamarul Arifin Muhamad by Muhamad, Kamarul Arifin

    Published 2002
    “…The method has been implemented as a C programming language. In this study, Wagner and Fischer algorithm, Hadith test collection that consists of Malay Hadith translation documents, query words and relevant judgements are used. …”
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    Thesis
  17. 17

    Topology-aware hypergraph based approach to optimize scheduling of parallel applications onto distributed parallel architectures by Koohi, Sina Zangbari

    Published 2020
    “…The first step lies at the modelling of parallel applications running on heterogeneous parallel computers. …”
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    Thesis
  18. 18

    Simulation of shortest path using a-star algorithm / Nurul Hani Nortaja by Nurul Hani , Nortaja

    Published 2004
    “…The steps to calculate a shortest path using A • algorithm is shown by using appropriate examples and related figures. …”
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    Thesis
  19. 19

    Implementation of Color Filtering on FPGA by Mohd Shukor, Mohd Nasir, Lo, H. H., Sebastian, Patrick

    Published 2007
    “…Verilog HDL is chosen as the hardware programming language for this system and its compiled using Quartus II program. …”
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    Conference or Workshop Item
  20. 20

    Improved black-winged kite algorithm and finite element analysis for robot parallel gripper design by Haohao, Ma, As’arry, Azizan, Yanwei, Feng, Lulu, Cheng, Delgoshaei, Aidin, Ismail, Mohd Idris Shah, Ramli, Hafiz Rashidi

    Published 2024
    “…This paper presents a comprehensive study on the design optimization of a robotic gripper, focusing on both the gripper modeling and the optimization of its parallel mechanism structure. This study integrates the Black-winged Kite Algorithm (BKA), Finite Element Analysis (FEA), Backpropagation Neural Network (BPNN), and response surface optimization techniques. …”
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    Article