Search Results - (((( programmable five array ) OR ( programmable same array ))) OR ( programmable rate array ))

Design of field programmable gate array-based proportional-integral-derivative fuzzy logic controller with tunable ganin by Obaid, Zeyad Assi

“…Many of fuzzy control applications require real-time operation; higher density programmable logic devices such as Field Programmable Gate Array (FPGA) can be used to integrate large amounts of logic in a single IC. …”
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Hardware Implementation Of Modified A5/1 Stream Cipher by Siti Yohana Akmal Mohd Fauzi, Kamaruzzaman Seman, Marinah Othman, Farrah Masyitah Mohd Shuib

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Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA by Shahadi H.I., Jidin R., Way W.H.

Design and implementation of real data fast fourier transform processor on field programmable gates array by Ahmed, Mohammed Kassim

“…Therefore, and for accurate comparison, this study aims to investigate the most common algorithms of RFFT on the same device and resources used. In this work, the memorybased FFT processor, based on radix-4 FFT algorithm is implemented on Cyclone II Field Programmable Gates Array (FPGA). …”
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Multi-directional matrix converter for low power application using field-programmable gate array by Toosi, Saman

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FPGA based Twofish Algorithm by Muhammad Imran, Ahmad, Mohd Nazrin, Md Isa, Abdul Halis, Abdul Aziz, Mohd Fisol, Osman

“…This paper presents the architecture of Twofish algorithm implemented with field programmable gate array (FPGA). Twofish is one of the five finalists in AES contest. …”
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Design method to transmit and receive source synchronous signals using source asynchronous by Ramachandran, Nathan

“…Cyclone V which is a low cost FPGA device supports LVDS IO channels for data rates up-till 1.25 Gigabit per second (Gbps) meanwhile the transceiver channels support data rates up-till 5 Gbps. …”
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Embedded System Real Time Data Acquisition System Using FPGA Technology for Detection and Counting of PD Signal from PICO Pulse Generator by Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Suhendi N.

Partial discharge detection system for counting PD signals in high voltage underground cable by using FPGA technology by Emilliano, Chakrabarty C.K., Ramasamy A.K., Ghani A.B.A.

“…Currently, FPGA (Field Programmable Gate Array) technology is being widely used for signal processing and control owing to its fast digital processing capability. …”

A customized floating-point processor design for FPGA and ASIC based thermal compensation in high-precision sensing by Sajjad, M., Yusoff, M.Z., Ahmed, M.

“…The signal processing techniques in the sensors are normally implemented using Field Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). …”
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Optimized Encoder Architecture for Structured Low Density Parity Check Codes of Short Length by Anggraeni, Silvia, Hussin, Fawnizu Azmadi, Jeoti , Varun

“…The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. …”
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Design of controller circuit for AC-to-DC three-phase inverter by using FPGA by Law Khang Ee

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Optimized encoder architecture for structured low density parity check codes of short length by Anggraeni, S., Hussin, F.A., Jeoti, V.

“…The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. …”
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Implementing universal priority DBA algorithm in PIC based EPON testbed by Radzi N.A.M., Din N.M., Al-Mansoori M.H., Zainol Abidin H.

“…Current testbed are based on Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA) which are not easily configurable. …”

Prototype of a Peak to Average Power Ratio Reduction Scheme in Orthogonal Frequency Division Multiplexing Systems by Varahram, P., Ali, B.M., Mohammady, S., Reza, A.W.

“…In this paper, a new crest factor reduction (CFR) scheme based on interleaved phase sequence called Dummy Sequence Insertion Enhanced Partial Transmit Sequence (DSI-EPTS) is proposed which effectively reduces the PAPR while at the same time keeps the total complexity low. Moreover, the prototype of the proposed scheme in field programmable gate array (FPGA) is demonstrated. …”
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FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices by Al-Shatari, M.O.A., Hussin, F.A., Aziz, A.A., Witjaksono, G., Tran, X.-T.

“…It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. …”
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Power Amplifiers Linearization Based On Complex Gain Memory Predistortion by Varahram, Pooria

“…This complex divider is then designed and implemented in Field Programmable Gate Array (FPGA) and combined with other parts to make the predistortion block. …”
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FPGA-enabled binarised convolutional neural networks toward real-time embedded object recognition system by Shuto, Daisuke, Abbas, Z., Sulaiman, N., Tamukoh, H.

“…In this presentation, we report the results of applying a binarised Convolutional Neural Network (CNN) and a Field Programmable Gate Array (FPGA) for image-based object recognition. …”
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New CFAR algorithm and circuit development for radar receiver by Kamal, Mustafa Subhi

“…The last MATLAB test for MSS-CA- vi CFAR with a spiky exponential model shown in Table 4.3 in chapter four shows clearly that MSS-CA-CFAR detects nine targets from ten that means the efficiency of detection of the proposed method is 90%. The field-programmable gate array FPGA chip that is used to implement the MSS-CA-CFAR algorithm needs only three signals from the radar receiver to match with the receiver circuit correctly which are time base clock signal period reset trigger signal and the pulse duration time.…”
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Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA by Al-Jewari, Maher Abd Ibrahim

“…This thesis reports the implementation of SVM in Cascaded H-Bridge Multilevel Inverter (CHMI) using Field Programmable Gate Arrays (FPGA) and analysis in-depth the performances of SVM computation on THD and fundamental component of output voltage. …”
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