Search Results - "NMOS devices"

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  1. 1
    Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device

    Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device by Fauziyah, Salehuddin

    Published 2009
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  2. 2
    Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device

    Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A.

    Published 2023
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  3. 3
    Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device

    Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device by Fauziyah , Salehuddin

    Published 2011
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  4. 4
    Impact of Different Dose and Angle in HALO Structure for 45nm NMOS Device

    Impact of Different Dose and Angle in HALO Structure for 45nm NMOS Device by Fauziyah, Salehuddin

    Published 2012
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  5. 5
    Effect of process parameter variations on threshold voltage in 45nm NMOS device

    Effect of process parameter variations on threshold voltage in 45nm NMOS device by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A.

    Published 2023
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  6. 6
    Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device

    Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device by Atan N.B., Ahmad I.B., Majlis B.B.Y., Fauzi I.B.A.

    Published 2023
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  7. 7
    Comparison study of lightly doped drain (LDD) and double diffused drain (DDD) to overcome hot carrier effect on 0.3um NMOS

    Comparison study of lightly doped drain (LDD) and double diffused drain (DDD) to overcome hot carrier effect on 0.3um NMOS by Muhammad, Mohd Khairi

    Published 2009
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  8. 8
    Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device

    Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A., Hashim U., Apte P.R.

    Published 2023
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  9. 9
    Impact of SALICIDE and Source/Drain Implants on Leakage Current and Sheet Resistance in 45nm NMOS Device

    Impact of SALICIDE and Source/Drain Implants on Leakage Current and Sheet Resistance in 45nm NMOS Device by Fauziyah, Salehuddin

    Published 2010
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  10. 10
    Impact of different dose and angle in HALO structure for 45nm NMOS device

    Impact of different dose and angle in HALO structure for 45nm NMOS device by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A.

    Published 2023
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  11. 11
    Development and optimization of Bi-GFET using Taguchi-based grey relational analysis with artificial neural network

    Development and optimization of Bi-GFET using Taguchi-based grey relational analysis with artificial neural network by Mohd Nizam, Nur Hazwani Naili

    Published 2024
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  12. 12
    Characterization of fabrication process noises for 32nm NMOS devices

    Characterization of fabrication process noises for 32nm NMOS devices by Elgomati H.A., Majlis B.Y., Ahmad I., Ziad T.

    Published 2023
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  13. 13
    Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

    Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Salehuddin F.

    Published 2023
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  14. 14
    Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET

    Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A., Elgomati H.A., Majlis B.Y.

    Published 2023
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  15. 15
    NMOS DEVICE OPTIMIZATION AND FABRICATION USING ATHENA & ATLAS SIMULATION SOFTWARE

    NMOS DEVICE OPTIMIZATION AND FABRICATION USING ATHENA & ATLAS SIMULATION SOFTWARE by CHOW , KIM POH

    Published 2004
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  16. 16
    Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.

    Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method. by Afifah Maheran A.H., Firhat E.N., Salehuddin F., Mohd Zain A.S., Ahmad I., Noor Faizah Z.A., Menon P.S., Elgomati H.A., Roslan A.F.

    Published 2023
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  17. 17
    Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

    Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A.

    Published 2023
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  18. 18
    Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array

    Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A., Hamid A.M.A., Menon P.S., Elgomati H.A., Majlis B.Y., Apte P.R.

    Published 2023
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  19. 19
    The Simulation of the Strained Si on Relaxed Si(o.7)Ge(0.3) N-MOS / Mohd Nurul Faizal Jusoh

    The Simulation of the Strained Si on Relaxed Si(o.7)Ge(0.3) N-MOS / Mohd Nurul Faizal Jusoh by Jusoh, Mohd Nurul Faizal

    Published 2006
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  20. 20
    Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage

    Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage by Elgomati H.A., Majlis B.Y., Salehuddin F., Ahmad I., Zaharim A., Hamid F.A.

    Published 2023
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