Modelling of process parameters for 32nm PMOS transistor using Taguchi method
As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transis...
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2023
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| author | Elgomati H.A. Majlis B.Y. Hamid A.M.A. Susthitha P.M. Ahmad I. |
| author2 | 36536722700 |
| author_facet | 36536722700 Elgomati H.A. Majlis B.Y. Hamid A.M.A. Susthitha P.M. Ahmad I. |
| author_sort | Elgomati H.A. |
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| content_provider | Universiti Tenaga Nasional |
| content_source | UNITEN Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transistor. Using Taguchi's experimental robust design strategy seven process parameters were assigned to 7 columns of the L18 orthogonal array to conduct 18 simulation runs. Fabrication of the 32nm PMOS transistor was simulated by using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. These simulators were used for computing Vth simulations for each row of the L18 array with 4 combinations of the 2 noise factors. Taguchi's nominal-the-best S/N ratio was used as the objective functions for the minimization of variance in Vth. The best settings of process parameters were determined using Analysis of Mean (ANOM) and Analysis of Variance (ANOVA) for reducing the variability of Vth. The best settings were used for verification simulations and the results showed that the Vth values had the least variance and the mean value could be adjusted to-0.103V +-0.003 for PMOS, which is well within ITRS specifications. � 2012 IEEE. |
| format | Conference paper |
| id | my.uniten.dspace-29521 |
| institution | Universiti Tenaga Nasional |
| publishDate | 2023 |
| record_format | dspace |
| spelling | my.uniten.dspace-295212023-12-28T14:30:20Z Modelling of process parameters for 32nm PMOS transistor using Taguchi method Elgomati H.A. Majlis B.Y. Hamid A.M.A. Susthitha P.M. Ahmad I. 36536722700 6603071546 36570222300 57201289731 12792216600 32nm PMOS ANOM ANOVA compensation implantations L18 orthogonal array Taguchi Method Threshold voltage Analysis of variance (ANOVA) CMOS integrated circuits Computer simulation Taguchi methods Threshold voltage 32nm PMOS Analysis of means ANOM Circuit performance CMOS technology Device parameters Electrical characterization Fabrication tool L18 orthogonal array Mean values Modelling of process Nanometer level Noise factor Objective functions pMOS transistors Process noise Process parameters Robust designs S/N ratio Taguchi Mathematical models As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transistor. Using Taguchi's experimental robust design strategy seven process parameters were assigned to 7 columns of the L18 orthogonal array to conduct 18 simulation runs. Fabrication of the 32nm PMOS transistor was simulated by using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. These simulators were used for computing Vth simulations for each row of the L18 array with 4 combinations of the 2 noise factors. Taguchi's nominal-the-best S/N ratio was used as the objective functions for the minimization of variance in Vth. The best settings of process parameters were determined using Analysis of Mean (ANOM) and Analysis of Variance (ANOVA) for reducing the variability of Vth. The best settings were used for verification simulations and the results showed that the Vth values had the least variance and the mean value could be adjusted to-0.103V +-0.003 for PMOS, which is well within ITRS specifications. � 2012 IEEE. Final 2023-12-28T06:30:20Z 2023-12-28T06:30:20Z 2012 Conference paper 10.1109/AMS.2012.22 2-s2.0-84866527184 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84866527184&doi=10.1109%2fAMS.2012.22&partnerID=40&md5=1fceca229dcf7ab301bcd180294b3885 https://irepository.uniten.edu.my/handle/123456789/29521 6243918 40 45 Scopus |
| spellingShingle | 32nm PMOS ANOM ANOVA compensation implantations L18 orthogonal array Taguchi Method Threshold voltage Analysis of variance (ANOVA) CMOS integrated circuits Computer simulation Taguchi methods Threshold voltage 32nm PMOS Analysis of means ANOM Circuit performance CMOS technology Device parameters Electrical characterization Fabrication tool L18 orthogonal array Mean values Modelling of process Nanometer level Noise factor Objective functions pMOS transistors Process noise Process parameters Robust designs S/N ratio Taguchi Mathematical models Elgomati H.A. Majlis B.Y. Hamid A.M.A. Susthitha P.M. Ahmad I. Modelling of process parameters for 32nm PMOS transistor using Taguchi method |
| title | Modelling of process parameters for 32nm PMOS transistor using Taguchi method |
| title_full | Modelling of process parameters for 32nm PMOS transistor using Taguchi method |
| title_fullStr | Modelling of process parameters for 32nm PMOS transistor using Taguchi method |
| title_full_unstemmed | Modelling of process parameters for 32nm PMOS transistor using Taguchi method |
| title_short | Modelling of process parameters for 32nm PMOS transistor using Taguchi method |
| title_sort | modelling of process parameters for 32nm pmos transistor using taguchi method |
| topic | 32nm PMOS ANOM ANOVA compensation implantations L18 orthogonal array Taguchi Method Threshold voltage Analysis of variance (ANOVA) CMOS integrated circuits Computer simulation Taguchi methods Threshold voltage 32nm PMOS Analysis of means ANOM Circuit performance CMOS technology Device parameters Electrical characterization Fabrication tool L18 orthogonal array Mean values Modelling of process Nanometer level Noise factor Objective functions pMOS transistors Process noise Process parameters Robust designs S/N ratio Taguchi Mathematical models |
| url_provider | http://dspace.uniten.edu.my/ |