H.I, S., R, J., W.H, W., & 54956597100. (2023). Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA. Elsevier Ltd.
Chicago Style (17th ed.) CitationH.I, Shahadi, Jidin R, Way W.H, and 54956597100. Concurrent Hardware Architecture for Dual-mode Audio Steganography Processor-based FPGA. Elsevier Ltd, 2023.
MLA (9th ed.) CitationH.I, Shahadi, et al. Concurrent Hardware Architecture for Dual-mode Audio Steganography Processor-based FPGA. Elsevier Ltd, 2023.
Warning: These citations may not always be 100% accurate.
