Low complexity multidimensional CDF 5/3 DWT architecture
This paper introduces an efficient low complexity multidimensional DWT architecture. The proposed architecture is based on a lifting-scheme for the Cohen-Daubechies-Feauveau (CDF) 5/3 DWT filter. It consists of low complexity identical computation and control units which can be used easily to implem...
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Institute of Electrical and Electronics Engineers Inc.
2023
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| _version_ | 1833412196008198144 |
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| author | Al-Azawi S. Abbas Y.A. Jidin R. |
| author2 | 36614945900 |
| author_facet | 36614945900 Al-Azawi S. Abbas Y.A. Jidin R. |
| author_sort | Al-Azawi S. |
| building | UNITEN Library |
| collection | Institutional Repository |
| content_provider | Universiti Tenaga Nasional |
| content_source | UNITEN Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | This paper introduces an efficient low complexity multidimensional DWT architecture. The proposed architecture is based on a lifting-scheme for the Cohen-Daubechies-Feauveau (CDF) 5/3 DWT filter. It consists of low complexity identical computation and control units which can be used easily to implement 2-D and 3-D DWT architectures. The synthesis results show that the output latency is 2N+2 clock cycles, with N2+2N+2 clock cycles required for the first level 2-D CDF 5/3 DWT computation. The architecture is parameterized to tackle various images and wordlength sizes. Furthermore, the proposed architecture is implemented using a Virtex 6 Xilinx FPGA platform. The implementation results reveal that the proposed architecture can operate at up to 198 MHz operating frequency. This reduces the time for first level DWT decomposition of a 512×512-pixel image to less than 1.3 m sec. © 2014 IEEE. |
| format | Conference Paper |
| id | my.uniten.dspace-21845 |
| institution | Universiti Tenaga Nasional |
| publishDate | 2023 |
| publisher | Institute of Electrical and Electronics Engineers Inc. |
| record_format | dspace |
| spelling | my.uniten.dspace-218452023-05-16T10:45:41Z Low complexity multidimensional CDF 5/3 DWT architecture Al-Azawi S. Abbas Y.A. Jidin R. 36614945900 56417806700 6508169028 This paper introduces an efficient low complexity multidimensional DWT architecture. The proposed architecture is based on a lifting-scheme for the Cohen-Daubechies-Feauveau (CDF) 5/3 DWT filter. It consists of low complexity identical computation and control units which can be used easily to implement 2-D and 3-D DWT architectures. The synthesis results show that the output latency is 2N+2 clock cycles, with N2+2N+2 clock cycles required for the first level 2-D CDF 5/3 DWT computation. The architecture is parameterized to tackle various images and wordlength sizes. Furthermore, the proposed architecture is implemented using a Virtex 6 Xilinx FPGA platform. The implementation results reveal that the proposed architecture can operate at up to 198 MHz operating frequency. This reduces the time for first level DWT decomposition of a 512×512-pixel image to less than 1.3 m sec. © 2014 IEEE. Final 2023-05-16T02:45:41Z 2023-05-16T02:45:41Z 2014 Conference Paper 10.1109/CSNDSP.2014.6923937 2-s2.0-84910614426 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84910614426&doi=10.1109%2fCSNDSP.2014.6923937&partnerID=40&md5=79cbb587d4b79241fe2951b9064d836e https://irepository.uniten.edu.my/handle/123456789/21845 6923937 804 808 Institute of Electrical and Electronics Engineers Inc. Scopus |
| spellingShingle | Al-Azawi S. Abbas Y.A. Jidin R. Low complexity multidimensional CDF 5/3 DWT architecture |
| title | Low complexity multidimensional CDF 5/3 DWT architecture |
| title_full | Low complexity multidimensional CDF 5/3 DWT architecture |
| title_fullStr | Low complexity multidimensional CDF 5/3 DWT architecture |
| title_full_unstemmed | Low complexity multidimensional CDF 5/3 DWT architecture |
| title_short | Low complexity multidimensional CDF 5/3 DWT architecture |
| title_sort | low complexity multidimensional cdf 5/3 dwt architecture |
| url_provider | http://dspace.uniten.edu.my/ |